Patent Assignment
Reel/Frame 064803/0387
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0208. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Recorded: 2023-09-01
Received: 2023-09-01
Pages: 19
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(55)
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MOLD UNDERFILL USING DISPENSING NEEDLE HAVING SAME WIDTH AS SEMICONDUCTOR DIE
App. No. 14/020,996
→
SEMICONDUCTOR DEVICE AND METHOD OF CONFINING CONDUCTIVE BUMP MATERIAL DURING REFLOW WITH SOLDER MASK PATCH
App. No. 13/905,845
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/896,608
→
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure
App. No. 13/845,329
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF
App. No. 13/791,375
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
App. No. 13/782,618
→
SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 13/727,116
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING REPASSIVATION LAYER WITH REDUCED OPENING TO CONTACT PAD OF SEMICONDUCTOR DIE
App. No. 13/664,626
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER SEMICONDUCTOR DIE MOUNTED TO TSV INTERPOSER
App. No. 13/571,020
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING MOLD FLASH PREVENTION TECHNOLOGY
App. No. 13/536,382
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REMOVABLE BACKING ELEMENT HAVING PLATED TERMINAL LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/536,321
→
SEMICONDUCTOR METHOD AND DEVICE OF FORMING A FAN-OUT POP DEVICE WITH PWB VERTICAL INTERCONNECT UNITS
App. No. 13/429,119
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO-VIAS PARTIALLY THROUGH INSULATING MATERIAL OVER BUMP INTERCONNECT CONDUCTIVE LAYER FOR STRESS RELIEF
App. No. 13/426,552
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING Z-INTERCONNECT CONDUCTIVE PILLARS WITH INNER POLYMER CORE
App. No. 13/405,094
→
SOLDER JOINT FLIP CHIP INTERCONNECTION
App. No. 13/367,214
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE
App. No. 13/366,560
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 13/345,589
→
Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief
App. No. 13/333,395
→
Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate
App. No. 13/324,349
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
App. No. 13/306,768
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/242,656
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STACKED SEMICONDUCTOR DIE AND CONDUCTIVE INTERCONNECT STRUCTURE THROUGH AN ENCAPSULANT
App. No. 13/234,902
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE MOLD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/235,202
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE
App. No. 13/197,215
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISLAND TERMINALS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/188,456
→
Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street
App. No. 13/171,341
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/165,658
→
METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT PACKAGING SYSTEM INCLUDING LASERING THROUGH ENCAPSULANT OVER INTERPOSER
App. No. 13/162,566
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ELECTRICAL INTERFACE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/102,047
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTED CIRCUIT LEAD ARRAY AND METHOD OF MANUFACTURE THEREOF
App. No. 13/102,044
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER ACTIVE SURFACE OF SEMICONDUCTOR DIE
App. No. 13/098,426
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER SHIELD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/071,228
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/069,980
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A THERMALLY REINFORCED SEMICONDUCTOR DIE
App. No. 13/052,588
→
Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections
App. No. 13/030,022
→
METHOD OF FABRICATING SEMICONDUCTOR DIE WITH THROUGH-HOLE VIA ON SAW STREETS AND THROUGH-HOLE VIA IN ACTIVE AREA OF DIE
App. No. 13/021,856
→
INTEGRATED CIRCUIT MOUNTING SYSTEM WITH PADDLE INTERLOCK AND METHOD OF MANUFACTURE THEREOF
App. No. 12/967,223
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/944,351
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PROTECTIVE COATING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/889,911
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF
App. No. 12/890,161
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL ALONG SLOPED SIDE SURFACE OF SEMICONDUCTOR DIE FOR Z-DIRECTION INTERCONNECT
App. No. 12/822,488
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING HIGH-ATTENUATION BALANCED BAND-PASS FILTER
App. No. 12/750,517
→
Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate
App. No. 12/726,880
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING TMV AND TSV IN WLCSP USING SAME CARRIER
App. No. 12/710,995
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP AND METHOD OF MANUFACTURE THEREOF
App. No. 12/629,879
→
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
App. No. 12/579,299
→
SEMICONDUCTOR DEVICE WITH A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
App. No. 12/572,590
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/563,475
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND TRANSPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/467,146
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-IN-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/404,279
→
Semiconductor Device and Method of Forming a Protective Layer on a Backside of the Wafer
App. No. 12/242,011
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE
App. No. 12/239,774
→
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/051,469
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/307,904
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FACE TO FACE STACK CONFIGURATION
App. No. 11/307,382
→