IP Library Granted Patent US 8,735,224
Granted Patent B2
US 8,735,224 · App. 13/102,044 · Granted May 27, 2014

Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof

Inventors: Byung Tai Do (Singapore, SG); Arnel Senosa Trasporto (Singapore, SG); Zigmund Ramirez Camacho (Singapore, SG)
Assignee: Stats Chippac Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,735,224
App. No.
13/102,044
Granted
May 27, 2014
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.

Claims (27)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a terminal having a top with a depression;

applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom is in direct contact with a peripheral portion at a plateau of the terminal;

forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and

connecting an integrated circuit to the terminal through the trace.

2. The method as claimed in claim 1 further comprising:

providing a die pad; and

applying a contact layer below the die pad; and

wherein:

forming the trace includes forming a perimeter trace around the die pad; and further comprising:

mounting the integrated circuit to the die pad.

3. The method as claimed in claim 1 further comprising mounting the integrated circuit above the trace extending beyond the integrated circuit.

4. The method as claimed in claim 1 wherein:

forming the trace includes forming multiple traces; and further comprising:

mounting the integrated circuit above the multiple traces terminating at a non-uniform distance from the integrated circuit.

5. The method as claimed in claim 1 further comprising mounting the integrated circuit above the trace extending below the integrated circuit from the terminal beyond the integrated circuit.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a terminal having a top with a plateau and a depression extending from the plateau to a maximum width, the terminal further having a bottom portion with a dent extending from the maximum width to a base;

applying a contact layer directly to the base of the terminal;

forming a dielectric material in the depression and in direct contact with the plateau and extending to the maximum width, the dielectric material having a gap formed therein and exposing a portion of the plateau therefrom is in direct contact with a peripheral portion at a plateau of the terminal;

forming a trace within the gap and in direct contact with the plateau, the trace extending laterally over an upper surface of the dielectric material;

connecting an integrated circuit to the terminal through the trace; and

encapsulating the trace and the integrated circuit with an encapsulation.

7. The method as claimed in claim 6 wherein applying the contact layer includes applying the contact layer directly to a portion of the dent of the terminal near the base leaving a portion of the dent near the maximum width exposed.

8. The method as claimed in claim 6 further comprising forming a dimpled surface in the terminal centered in the base.

9. The method as claimed in claim 6 further comprising forming solder balls below the base and attached to the contact layer.

10. The method as claimed in claim 6 wherein connecting the integrated circuit to the terminal includes connecting the integrated circuit with a bond wire or with a solder ball.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0208. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0387 →
RELEASE OF SECURITY INTEREST Recorded Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0208 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2011
From: DO, BYUNG TAI; TRASPORTO, ARNEL SENOSA; CAMACHO, ZIGMUND RAMIREZ
To: STATS CHIPPAC LTD.
Reel/Frame 026286/0758 →
Continuity (2)
Provisional Application 61442797 · Feb 14, 2011
Related Publication 20120280390A1 · Nov 8, 2012