Stacked integrated circuit package system with face to face stack configuration

1. A method for manufacturing a stacked integrated circuit package system comprising:

forming a first molded chip comprises:

attaching a conductor on a die,

applying an encapsulant around the conductor, and

exposing a surface of the conductor in the encapsulant with a plane formed by all of the exposed portion coplanar to a plane formed by a side of the encapsulant opposite the die;

attaching a first electrical interconnect on the conductor of the first molded chip; and

stacking an integrated circuit device on the first molded chip with an electrical connector of the integrated circuit device connected to the conductor of the first molded chip with the first electrical interconnect.

2. The method as claimed in claim 1 wherein stacking the integrated circuit device on the first molded chip comprises forming a second molded chip having a similar structure to the first molded chip.

3. The method as claimed in claim 1 wherein stacking the integrated circuit device on the first molded chip comprises:

forming a package having an integrated circuit die on a carrier;

connecting a bond wire to the integrated circuit die and carrier;

attaching the electrical connector to the carrier on a side opposite of the integrated circuit die; and

encapsulating a molding compound around the integrated circuit die, the bond wire, and a top of the carrier.

4. The method as claimed in claim 1 wherein stacking the integrated circuit device on the first molded chip comprises applying a spacer adhesive between the first molded chip and the integrated circuit device.

5. The method as claimed in claim 1 further comprising:

attaching a third molded chip on the integrated circuit device;

attaching a second electrical interconnect to the conductor of the third molded chip; and

stacking a fourth molded chip on the third molded chip with the conductor of the fourth molded chip connected to the conductor of the third molded chip with the second electrical interconnect.

6. A method for manufacturing a stacked integrated circuit package system comprising:

forming a first molded chip comprises:

attaching conductors on an active side of a wafer,

applying a top mold around the conductors on the active side,

exposing a surface of the conductors in the top mold, and

singulating integrated circuit dies from the wafer, the integrated circuit dies have the conductors surrounded by the top mold with a plane formed by all of the exposed portion of the conductors coplanar to a plane formed by a side of the top mold opposite the die;

attaching electrical interconnects on the conductors of the first molded chip; and

stacking an integrated circuit device on the first molded chip with electrical connectors of the integrated circuit device connected to the conductors of the first molded chip with the electrical interconnects.

7. The method as claimed in claim 6 wherein attaching the electrical interconnects on the conductors comprises:

attaching wire stitches on the conductors of the first molded chip; and

forming bumps on the wire stitches.

8. The method as claimed in claim 6 wherein attaching the electrical interconnects to the conductors comprises attaching the electrical interconnects to a substrate.

9. The method as claimed in claim 6 further comprising molding an encapsulant around the first molded chip, the integrated circuit device, and the electrical interconnects.

10. The method as claimed in claim 6 wherein attaching the conductors on the active side of the wafer comprises attaching solder bumps on the active side of the wafer.