Patent Assignment
Reel/Frame 038378/0418
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 9
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(80)
Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate
App. No. 13/870,928
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DIE WITH ACTIVE REGION RESPONSIVE TO EXTERNAL STIMULUS
App. No. 13/853,969
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
App. No. 13/846,742
→
PACKAGE-IN-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS
App. No. 13/845,409
→
Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP
App. No. 13/845,542
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE LEADS FROM BASE SUBSTRATE AS STANDOFF FOR STACKING SEMICONDUCTOR DIE
App. No. 13/846,014
→
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure
App. No. 13/845,329
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
App. No. 13/832,333
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
App. No. 13/782,618
→
Integrated Passive Devices
App. No. 13/782,939
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SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A LOW PROFILE EMBEDDED WAFER LEVEL BALL GRID ARRAY MOLDED LASER PACKAGE (EWLB-MLP)
App. No. 13/772,683
→
Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration
App. No. 13/771,825
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOLDING
App. No. 13/769,302
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
App. No. 13/768,862
→
LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
App. No. 13/766,646
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
App. No. 13/766,493
→
Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
App. No. 13/765,478
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECT STRUCTURE ON LEADFRAME
App. No. 13/765,594
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
App. No. 13/760,187
→
Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die
App. No. 13/732,150
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SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS
App. No. 13/728,012
→
SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 13/727,116
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY IN BUILD-UP INTERCONNECT STRUCTURE FOR SHORT SIGNAL PATH BETWEEN DIE
App. No. 13/726,467
→
Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection
App. No. 13/720,516
→
Semiconductor Device and Method of Forming Directional RF Coupler with IPD for Additional RF Signal Processing
App. No. 13/716,799
→
Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect
App. No. 13/715,424
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED MULTI-DIE LEADFRAME FOR ELECTRICAL INTERCONNECT OF STACKED SEMICONDUCTOR DIE
App. No. 13/691,464
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS AND HEAT SINK OVER SEMICONDUCTOR DIE USING LEADFRAME
App. No. 13/683,946
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS EMBEDDED IN PHOTOSENSITIVE ENCAPSULANT
App. No. 13/683,884
→
Semiconductor Device and Method of Forming Insulating Layer on Conductive Traces for Electrical Isolation in Fine Pitch Bonding
App. No. 13/682,510
→
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING Z-DIRECTION CONDUCTIVE POSTS EMBEDDED IN STRUCTURALLY PROTECTIVE ENCAPSULANT
App. No. 13/682,281
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RF FEM WITH LC FILTER AND IPD FILTER OVER SUBSTRATE
App. No. 13/678,134
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT IN FO-WLCSP USING LEADFRAME DISPOSED BETWEEN SEMICONDUCTOR DIE
App. No. 13/645,385
→
FLIP CHIP INTERCONNECTION HAVING NARROW INTERCONNECTION SITES ON THE SUBSTRATE
App. No. 13/645,397
→
Method of Forming an Inductor on a Semiconductor Wafer
App. No. 13/622,280
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH CAVITIES FORMED THROUGH ETCH-RESISTANT CONDUCTIVE LAYER FOR BUMP LOCKING
App. No. 13/622,297
→
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
App. No. 13/621,810
→
SEMICONDUCTOR DEVICE WITH SOLDER BUMP FORMED ON HIGH TOPOGRAPHY PLATED CU PADS
App. No. 13/621,804
→
Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die
App. No. 13/609,050
→
Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump
App. No. 13/609,003
→
Semiconductor Device and Method of Forming FO-WLCSP with Discrete Semiconductor Components Mounted Under and Over Semiconductor Die
App. No. 13/607,204
→
Semiconductor Device and Method of Forming a Conductive Via-in-Via Structure
App. No. 13/604,539
→
Semicinductor Device with Cross-Talk Isolation Using M-CAP
App. No. 13/572,517
→
Semiconductor Device and Method of Forming WLCSP Structure using Protruded MLP
App. No. 13/570,979
→
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SEMICONDUCTOR DIE IN MOLD LASER PACKAGE INTERCONNECTED BY BUMPS AND CONDUCTIVE VIAS
App. No. 13/566,872
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Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus
App. No. 13/545,887
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE
App. No. 13/478,008
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLAR HAVING AN EXPANDED BASE
App. No. 13/468,981
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NON-LINEAR INTERCONNECT LAYER WITH EXTENDED LENGTH FOR JOINT RELIABILITY
App. No. 13/417,034
→
Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure
App. No. 13/366,008
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING EXTENDED SEMICONDUCTOR DEVICE WITH FAN-OUT INTERCONNECT STRUCTURE TO REDUCE COMPLEXITY OF SUBSTRATE
App. No. 13/336,860
→
Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief
App. No. 13/333,395
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE WITH CONDUCTIVE MICRO VIA ARRAY FOR 3-D FO-WLCSP
App. No. 13/326,128
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM STRUCTURE ON BACK SURFACE OF TSV SEMICONDUCTOR WAFER
App. No. 13/324,446
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Semiconductor Device and Method of Forming Recesses in Conductive Layer to Detect Continuity for Interconnect Between Semiconductor Die and Substrate
App. No. 13/324,397
→
Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate
App. No. 13/324,349
→
SEMICONDUCTOR DEVICE AND METHOD OF MAKING SINGLE LAYER SUBSTRATE WITH ASYMMETRICAL FIBERS AND REDUCED WARPAGE
App. No. 13/314,984
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THICK ENCAPSULANT FOR STIFFNESS WITH RECESSES FOR STRESS RELIEF IN FO-WLCSP
App. No. 13/315,010
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING GUARD RING AROUND CONDUCTIVE TSV THROUGH SEMICONDUCTOR WAFER
App. No. 13/315,033
→
Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration
App. No. 13/312,730
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL UNDER BUMP FOR ELECTRICAL CONNECTION TO ENCLOSED BUMP
App. No. 13/307,849
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SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYER OVER SUBSTRATE WITH VENTS TO CHANNEL BUMP MATERIAL AND REDUCE INTERCONNECT VOIDS
App. No. 13/303,019
→
Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer
App. No. 13/289,811
→
SEMICONDUCTOR DIE AND METHOD OF FORMING SLOPED SURFACE IN PHOTORESIST LAYER TO ENHANCE FLOW OF UNDERFILL MATERIAL BETWEEN SEMICONDUCTOR DIE AND SUBSTRATE
App. No. 13/287,006
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THERMAL INTERFACE MATERIAL AND HEAT SPREADER OVER SEMICONDUCTOR DIE
App. No. 13/287,035
→
Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP
App. No. 13/243,558
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/242,656
→
Semiconductor Device and Method of Forming Interconnect Substrate for FO-WLCSP
App. No. 13/243,214
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE
App. No. 13/239,080
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR PACKAGE USING PANEL FORM CARRIER
App. No. 13/236,952
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A RECONFIGURED STACKABLE WAFER LEVEL PACKAGE WITH VERTICAL INTERCONNECT
App. No. 13/234,535
→
Semiconductor Device and Method of Forming Conductive Protrusions Over Conductive Pillars or Bond Pads as Fixed Offset Vertical Interconnect Structure
App. No. 13/234,366
→
Semiconductor Device and Method of Forming a Low Profile Dual-Purpose Shield and Heat-Dissipation Structure
App. No. 13/226,767
→
Semiconductor device and method of forming FO-WLCSP with recessed interconnect area in peripheral region of semiconductor die
App. No. 13/225,683
→
Semiconductor Device and Method of Forming TIM Within Recesses of MUF Material
App. No. 13/218,388
→
Semiconductor Device and Method of Forming a Stackable Semiconductor Package with Vertically-Oriented Discrete Electrical Devices as Interconnect Structures
App. No. 13/208,027
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Semiconductor Device and Method of Forming POP With Stacked Semiconductor Die and Bumps Formed Directly on the Lower Die
App. No. 13/195,636
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
App. No. 13/167,566
→
Semiconductor Device and Method of Forming RF FEM and RF Transceiver in Semiconductor Package
App. No. 13/163,026
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Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity Region
App. No. 13/149,628
→