Semiconductor device and method of forming Fo-WLCSP with recessed interconnect area in peripheral region of semiconductor die
A semiconductor device has a temporary layer, such as a dam material or adhesive layer, formed over a carrier. A plurality of recesses is formed in the temporary layer. A first semiconductor die is mounted within the recesses of the temporary layer. An encapsulant is deposited over the first semiconductor die and temporary layer. The encapsulant extends into the recesses in the temporary layer. The carrier and temporary layer are removed to form recessed interconnect areas around the first semiconductor die. Alternatively, the recessed interconnect areas can be formed the carrier or encapsulant. Multiple steps can be formed in the recesses of the temporary layer. A conductive layer is formed over the first semiconductor die and encapsulant and into the recessed interconnect areas. A second semiconductor die can be mounted on the first semiconductor die. The semiconductor device can be integrated into PiP and Fi-PoP arrangements.
1. A semiconductor device, comprising:
a first semiconductor die including an active surface, a back surface opposite the active surface, and side surfaces between the active surface and back surface;
a first encapsulant deposited in continuous contact with the back surface and side surfaces of the first semiconductor die and including a recessed interconnect area including a sidewall and horizontal portion of the first encapsulant in a peripheral region outside a footprint of the first semiconductor die, wherein the horizontal portion of the first encapsulant extends from the sidewall to an edge of the semiconductor device;
a first conductive layer formed over the first semiconductor die and first encapsulant and extending from a contact pad of the first semiconductor die along the sidewall and over the horizontal portion of the first encapsulant within the recessed interconnect area;
a second conductive layer formed over the first semiconductor die and first encapsulant and extending from an area over the active surface electrically isolated from the first semiconductor die along the sidewall and over the horizontal portion of the first encapsulant within the recessed interconnect area; and
an interconnect structure formed on the first conductive layer on the horizontal portion of the first encapsulant in the recessed interconnect area, wherein the interconnect structure is separated from a portion of the first conductive layer on the sidewall of the first encapsulant.
2. The semiconductor device of claim 1 , further including a plurality of bumps formed between the contact pads of the first semiconductor die and the first conductive layer.
3. The semiconductor device of claim 1 , wherein the interconnect structure includes a bump or bond wire.
4. The semiconductor device of claim 1 , further including:
a second semiconductor die disposed within the first encapsulant over the first semiconductor die; and
a plurality of bumps formed between contact pads of the second semiconductor die and the first conductive layer or the second conductive layer formed over the horizontal portion of the first encapsulant within the recessed interconnect area.
5. A semiconductor device, comprising:
a first semiconductor die;
a first encapsulant deposited around side surfaces of the first semiconductor die and including a recessed interconnect area including a sidewall and horizontal portion of the first encapsulant in a peripheral region outside a footprint of the first semiconductor die, wherein the horizontal portion of the first encapsulant extends from the sidewall to an edge of the semiconductor device;
a first conductive layer formed over the first semiconductor die and first encapsulant and extending from a contact pad of the first semiconductor die along the sidewall and over the horizontal portion of the first encapsulant within the recessed interconnect area; and
a second conductive layer formed over the first semiconductor die and first encapsulant and extending from an area over the active surface electrically isolated from the first semiconductor die along the sidewall and over the horizontal portion of the first encapsulant within the recessed interconnect area.
6. The semiconductor device of claim 5 , further including an interconnect structure formed on the first conductive layer on the horizontal portion of the first encapsulant in the recessed interconnect area, wherein the interconnect structure is separated from a portion of the first conductive layer on the sidewall of the first encapsulant.
7. The semiconductor device of claim 6 , wherein the interconnect structure includes a bump or bond wire.
8. The semiconductor device of claim 5 , further including a plurality of bumps formed between the contact pads of the first semiconductor die and the first conductive layer.
9. The semiconductor device of claim 5 , further including:
a second semiconductor die disposed within the first encapsulant over the first semiconductor die; and
a plurality of bumps formed between contact pads of the second semiconductor die and the first conductive layer or the second conductive layer formed over the horizontal portion of the first encapsulant within the recessed interconnect area.
10. A semiconductor device, comprising:
a first semiconductor die;
a first encapsulant deposited around side surfaces of the first semiconductor die and including a recessed interconnect area including a sidewall and horizontal portion of the first encapsulant in a peripheral region outside a footprint of the first semiconductor die, wherein the horizontal portion of the first encapsulant extends from the sidewall to an edge of the semiconductor device;
a first conductive layer formed over the first semiconductor die and first encapsulant and extending from a contact pad of the first semiconductor die along the sidewall and over the horizontal portion of the first encapsulant within the recessed interconnect area; and
an interconnect structure formed on the first conductive layer on the horizontal portion of the first encapsulant in the recessed interconnect area, wherein the interconnect structure is separated from a portion of the first conductive layer on the sidewall of the first encapsulant.
11. The semiconductor device of claim 10 , further including a second conductive layer formed over the first semiconductor die and first encapsulant and extending from an area over the active surface electrically isolated from the first semiconductor die along the sidewall and over the horizontal portion of the first encapsulant within the recessed interconnect area.
12. The semiconductor device of claim 10 , wherein the interconnect structure includes a bump or bond wire.
13. The semiconductor device of claim 10 , further including a plurality of bumps formed between the contact pads of the first semiconductor die and the first conductive layer.
14. The semiconductor device of claim 10 , further including a second semiconductor die disposed within the first encapsulant over the first semiconductor die.
15. A semiconductor device, comprising:
a first semiconductor die;
an encapsulant deposited around side surfaces of the first semiconductor die and including a recessed interconnect area including a sidewall and horizontal portion of the encapsulant in a peripheral region outside a footprint of the first semiconductor die, wherein the horizontal portion of the encapsulant extends from the sidewall to an edge of the semiconductor device; and
a first conductive layer formed over the first semiconductor die and encapsulant and extending from a contact pad of the first semiconductor die along the sidewall and over the horizontal portion of the encapsulant within the recessed interconnect area.
16. The semiconductor device of claim 15 , further including a second conductive layer formed over the first semiconductor die and encapsulant and extending from an area over the active surface electrically isolated from the first semiconductor die along the sidewall and over the horizontal portion of the encapsulant within the recessed interconnect area.
17. The semiconductor device of claim 15 , further including an interconnect structure formed on the first conductive layer on the horizontal portion of the encapsulant in the recessed interconnect area, wherein the interconnect structure is separated from a portion of the first conductive layer on the sidewall of the encapsulant.
18. The semiconductor device of claim 15 , further including a plurality of bumps formed between the contact pads of the first semiconductor die and the first conductive layer.
19. The semiconductor device of claim 15 , further including a second semiconductor die disposed within the encapsulant over the first semiconductor die.