Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM inspection
View Patent ↗A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers.
1. A semiconductor device, comprising:
a semiconductor die including an active surface and back surface opposite the active surface of the semiconductor die;
an interconnect structure formed over the active surface of the semiconductor die; and
an encapsulant formed over the semiconductor die with a first exterior surface of the encapsulant contacting the interconnect structure and a second exterior surface of the encapsulant opposite the first exterior surface, wherein the second exterior surface of the encapsulant comprises a first roughness and a first average thickness outside a footprint of the semiconductor die and a second roughness and a second average thickness over the back surface of the semiconductor die including a difference between a high region and low region of less than 1.0 micrometers, the first average thickness of the encapsulant greater than the second average thickness of the encapsulant, and a surface of the semiconductor device coplanar with the second exterior surface of the encapsulant being electrically isolated from the interconnect structure.
2. The semiconductor device of claim 1 , wherein a difference between the first average thickness and second average thickness is less than or equal to 10 micrometers.
3. The semiconductor device of claim 1 , wherein the first roughness is offset from the second roughness by less than ten micrometers.
4. A semiconductor device, comprising:
a semiconductor die;
an interconnect structure formed over the semiconductor die; and
an encapsulant formed over and around the semiconductor die, wherein a surface of the encapsulant opposite the interconnect structure comprises a first portion including a first surface roughness and a first average thickness around the semiconductor die and a second portion including a second surface roughness and a second average thickness over the semiconductor die, the second surface roughness less than the first surface roughness and the first average thickness of the encapsulant greater than the second average thickness of the encapsulant.
5. The semiconductor device of claim 4 , wherein a difference between the first average thickness and second average thickness is less than or equal to 10 micrometers.
6. The semiconductor device of claim 4 , wherein the second surface roughness includes a difference between a high region and low region of less than 1.0 micrometers.
7. The semiconductor device of claim 4 , wherein the first surface roughness includes a difference between a high region and low region of greater than 1.2 micrometers.
8. The semiconductor device of claim 4 , wherein the interconnect structure is formed over an active surface of the semiconductor die.
9. The semiconductor device of claim 4 , wherein the first surface roughness is offset from the second surface roughness by less than ten micrometers.
10. A semiconductor device, comprising:
a semiconductor die including an active surface and a back surface opposite the active surface; and
an encapsulant formed over and around the semiconductor die, wherein a surface of the encapsulant covers the back surface of the semiconductor die and comprises a first roughness and a first average thickness around the semiconductor die and a second roughness different from the first roughness and a second average thickness over the back surface of the semiconductor die, the first average thickness of the encapsulant greater than the second average thickness of the encapsulant.
11. The semiconductor device of claim 10 , wherein a difference between the first average thickness and second average thickness is less than or equal to 10 micrometers.
12. The semiconductor device of claim 10 , wherein the second roughness includes a difference between a high region and low region of less than 1.0 micrometers.
13. The semiconductor device of claim 10 , wherein the first roughness includes a difference between a high region and low region of the first roughness of greater than 1.2 micrometers.
14. The semiconductor device of claim 10 , further including an interconnect structure formed over the active surface of the semiconductor die.
15. The semiconductor device of claim 10 , further including a plurality of bumps formed over the semiconductor die.
16. The semiconductor device of claim 10 , wherein the first roughness is offset from the second roughness by less than ten micrometers.