Solder bump with inner core pillar in semiconductor package
A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.
1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a first conductive layer over the substrate;
forming a single core pillar over the first conductive layer with the single core pillar including a width less than a width of the first conductive layer;
forming a second conductive layer conformally over the single core pillar and first conductive layer, wherein the second conductive layer extends into a hollow interior region of the single core pillar;
forming a third conductive layer conformally over the second conductive layer; and
forming a bump over a side surface of the single core pillar.
2. The method of claim 1 , further including forming an under bump metallization (UBM) layer over the first conductive layer prior to forming the single core pillar.
3. The method of claim 2 , wherein forming the UBM layer includes:
forming a fourth conductive layer over the first conductive layer; and
forming a fifth conductive layer over the fourth conductive layer.
4. The method of claim 1 , wherein the width of the single core pillar is 40-60% of a width of the bump.
5. The method of claim 1 , wherein the core pillar includes copper or nickel.
6. A semiconductor device, comprising:
a substrate;
a first conductive layer formed over the substrate;
a single core pillar formed over the first conductive layer with the single core pillar including a width less than a width of the first conductive layer;
a second conductive layer formed conformally over the single core pillar and first conductive layer, wherein the second conductive layer extends into a hollow interior region of the single core pillar;
a third conductive layer formed conformally over the second conductive layer; and
a bump formed over a side surface of the single core pillar.
7. The semiconductor device of claim 6 , further including forming an under bump metallization layer over the first conductive layer.
8. The semiconductor device of claim 6 , wherein the single core pillar includes copper or nickel.
9. A semiconductor device, comprising:
a substrate;
a first conductive layer formed over the substrate;
a core pillar formed over the first conductive layer;
a second conductive layer formed conformally over the core pillar and within a hollow interior region of the core pillar; and
a bump formed over the core pillar and within the hollow interior region of the core pillar.
10. The semiconductor device of claim 9 , further including a third conductive layer formed over the second conductive layer.
11. The semiconductor device of claim 9 , further including an under bump metallization (UBM) layer formed over the first conductive layer.
12. The semiconductor device of claim 9 , wherein the core pillar includes copper or nickel.
13. The semiconductor device of claim 9 , wherein a width of the core pillar is 40-60% of a width of the bump.
14. The semiconductor device of claim 9 , wherein the core pillar includes a rectangular, cylindrical, or toroidal shape.
15. A semiconductor device, comprising:
a substrate;
a first conductive layer formed over the substrate;
an under bump metallization (UBM) layer formed over the first conductive layer;
a single core pillar formed over the UBM layer;
a second conductive layer formed over the single core pillar and along the UBM layer, wherein the second conductive layer extends into a hollow interior region of the single core pillar; and
a bump formed over the single core pillar and second conductive layer.
16. The semiconductor device of claim 15 , further including a third conductive layer formed over the second conductive layer.
17. The semiconductor device of claim 15 , wherein the UBM layer includes:
a third conductive layer formed over the first conductive layer;
a fourth conductive layer formed over the third conductive layer; and
a fifth conductive layer formed over the fourth conductive layer.
18. The semiconductor device of claim 15 , wherein a width of the single core pillar is 40-60% of a width of the bump.
19. The semiconductor device of claim 15 , wherein the single core pillar includes copper or nickel.
20. The semiconductor device of claim 15 , wherein the single core pillar includes a height of at least two-thirds of a height of the bump.
21. A semiconductor device, comprising:
a substrate;
a first conductive layer formed over the substrate;
a core pillar formed over the first conductive layer with the core pillar including a width less than a width of the first conductive layer;
a second conductive layer formed over the core pillar with the second conductive layer extending into an interior region of the core pillar;
a third conductive layer formed over the second conductive layer; and
a bump formed around the core pillar.
22. The semiconductor device of claim 21 , further including the bump formed within the interior region of the core pillar.
23. The semiconductor device of claim 21 , further including:
a fourth conductive layer formed over the first conductive layer; and
a fifth conductive layer formed over the fourth conductive layer.
24. The semiconductor device of claim 23 , further including the core pillar formed over the fifth conductive layer.
25. The semiconductor device of claim 21 , wherein the width of the core pillar is 40-60% of a width of the bump.