IP Library Granted Patent US 9,293,401
Granted Patent B2
US 9,293,401 · App. 13/772,683 · Granted Mar 22, 2016

Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)

Inventors: Seung Wook Yoon (Singapore, SG); Jose A. Caparas (Singapore, SG); Yaojian Lin (Singapore, SG); Pandi C. Marimuthu (Singapore, SG); Kang Chen (Singapore, SG); Xusheng Bao (Singapore, SG); Jianmin Fang (Singapore, SG)
Assignee: STATS ChipPAC, Ltd.
H01L23/49811H01L21/56H01L21/561H01L24/19H01L24/96H01L24/97H01L21/568H01L23/3128H01L2224/12105H01L2224/97H01L2225/1035H01L2225/1058H01L2924/01322H01L2924/12041H01L2924/12042H01L2924/1306H01L2924/13091H01L2924/181
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Quick Facts
Patent No.
US 9,293,401
App. No.
13/772,683
Granted
Mar 22, 2016
Kind
B2
Abstract

A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.

Claims (50)

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant over and around the semiconductor die including a first surface of the encapsulant coplanar with an active surface of the semiconductor die;

planarizing the encapsulant to form a planar second surface of the encapsulant opposite the first surface of the encapsulant;

forming an interconnect structure under the first surface of the encapsulant and in physical contact with the active surface of the semiconductor die after depositing the encapsulant;

forming an opening from the planar second surface of the encapsulant extending to and terminating at the first surface of the encapsulant coplanar with the active surface of the semiconductor die;

depositing a bump material over the opening of the encapsulant; and

reflowing the bump material to form a bump recessed within the opening and contacting the interconnect structure.

2. The method of claim 1 , further including:

providing a semiconductor package; and

disposing the semiconductor package over the encapsulant and electrically connecting the semiconductor package to the bump.

3. The method of claim 1 , further including forming a plurality of bumps under the interconnect structure.

4. The method of claim 2 , wherein the semiconductor package includes a memory device.

5. The method of claim 1 , wherein the semiconductor device includes a height less than 1 millimeter.

6. The method of claim 1 , wherein the opening includes a tapered sidewall formed by laser direct ablation.

7. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant over and around the semiconductor die including a first surface of the encapsulant coplanar with an active surface of the semiconductor die and a planar second surface of the encapsulant opposite the first surface of the encapsulant;

forming an interconnect structure under the first surface of the encapsulant after depositing the encapsulant;

forming an opening in the planar second surface of the encapsulant;

and

forming a bump recessed within the opening of the encapsulant.

8. The method of claim 7 , wherein forming the interconnect structure further includes forming the interconnect structure under the semiconductor die.

9. The method of claim 8 , wherein the semiconductor die and bump material are electrically connected to the interconnect structure.

10. The method of claim 7 , further including:

providing a semiconductor package; and

disposing the semiconductor package over the semiconductor die and encapsulant.

11. The method of claim 7 , further including forming a plurality of bumps under the interconnect structure.

12. The method of claim 7 , further including forming of the opening by laser direct ablation.

13. A semiconductor device, comprising:

a semiconductor die;

an encapsulant disposed over and around the semiconductor die including a first surface of the encapsulant coplanar with an active surface of the semiconductor die and a planar second surface of the encapsulant opposite the first surface of the encapsulant and over a second surface of the semiconductor die opposite the active surface;

an insulating layer formed under the first surface of the encapsulant including a first opening formed in the insulating layer;

a conductive layer disposed under the insulating layer and in the first opening with a second opening formed in the planar surface of the encapsulant extending to the conductive layer; and

a bump formed over the conductive layer and recessed within the second opening.

14. The semiconductor device of claim 13 , further including a semiconductor package disposed over the encapsulant and electrically connected to the bump.

15. The semiconductor device of claim 13 , wherein the semiconductor device includes a height less than 1 millimeter.

16. The semiconductor device of claim 13 , further including a plurality of interconnect structures disposed under the conductive layer.

17. The semiconductor device of claim 13 , wherein the second opening includes a tapered sidewall.

18. A method of making a semiconductor device, comprising:

providing a substrate;

depositing an encapsulant over and around the substrate including a first surface of the encapsulant coplanar with a first surface of the substrate and a planar second surface of the encapsulant opposite the first surface of the encapsulant;

forming an interconnect structure under the first surface of the encapsulant after depositing the encapsulant; and

forming an opening in the planar second surface of the encapsulant.

19. The method of claim 18 , wherein forming the interconnect structure further includes forming the interconnect structure under the substrate.

20. The method of claim 18 , further including:

providing a semiconductor package; and

disposing the semiconductor package over the substrate and encapsulant.

21. The method of claim 18 , further including forming of the opening in the encapsulant by laser direct ablation.

22. The method of claim 1 , further including forming the opening in the encapsulant by laser direct ablation.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED ON REEL 038378 FRAME 0418. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064908/0920 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0418 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2014
From: CHEN, KANG; BAO, XUSHENG; FANG, JIANMIN
To: STATS CHIPPAC, LTD.
Reel/Frame 034604/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2013
From: YOON, SEUNG WOOK; CAPARAS, JOSE A.; LIN, YAOJIAN; MARIMUTHU, PANDI C.
To: STATS CHIPPAC, LTD.
Reel/Frame 029848/0981 →
Continuity (7)
Continuation In Part 13191318 · Jul 26, 2011
Continuation In Part 12572590 · Oct 2, 2009
Division 12333977 · Dec 12, 2008
Provisional Application 61606327 · Mar 2, 2012
Provisional Application 61441561 · Feb 10, 2011
Provisional Application 61444914 · Feb 21, 2011
Related Publication 20130228917A1 · Sep 5, 2013