IP Library Patent Application 13609050
Patent Application
App. No. 13/609,050

Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
13/609,050
Abstract

A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure.

Claims (41)

1 . A semiconductor device, comprising:

a substrate including a plurality of bodies extending from the substrate;

a first semiconductor die disposed over the substrate between the bodies;

an encapsulant deposited over the first semiconductor die and substrate and around the bodies of the substrate; and

an interconnect structure formed over the encapsulant and extending to the bodies of the substrate.

2 . The semiconductor device of claim 1 , wherein the substrate includes a base plate with the bodies extending from the base plate.

3 . The semiconductor device of claim 1 , wherein the encapsulant is planarized to expose the first semiconductor die.

4 . The semiconductor device of claim 1 , further including a plurality of openings in the encapsulant to expose the bodies of the substrate and contact pads of the first semiconductor die.

5 . The semiconductor device of claim 1 , wherein the substrate is removed to expose the interconnect structure.

6 . The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die.

7 . A semiconductor device, comprising:

a substrate including a plurality of bodies;

a first semiconductor die disposed over the substrate;

an encapsulant deposited over the first semiconductor die and substrate; and

an interconnect structure formed over the encapsulant and extending to the bodies of the substrate.

8 . The semiconductor device of claim 7 , wherein the substrate includes a base plate with the bodies extending from the base plate.

9 . The semiconductor device of claim 7 , further including a plurality of openings in the encapsulant to expose the bodies of the substrate.

10 . The semiconductor device of claim 9 , further including a conductive layer disposed over the encapsulant and into the openings and electrically connected to the interconnect structure.

11 . The semiconductor device of claim 7 , wherein the substrate is removed to expose the interconnect structure.

12 . The semiconductor device of claim 7 , further including a second semiconductor die disposed over the first semiconductor die.

13 . The semiconductor device of claim 7 , further including a plurality of conductive vias formed through the first semiconductor die.

14 . A semiconductor device, comprising:

a first semiconductor die;

an encapsulant deposited over the first semiconductor die; and

an interconnect structure formed over and partially through a first surface of the encapsulant, the interconnect structure being electrically connected to the first semiconductor die, wherein the encapsulant includes a plurality of openings in a second surface of the encapsulant opposite the first surface of the encapsulant and extending to the interconnect structure.

15 . The semiconductor device of claim 14 , further including a second semiconductor die disposed over the first semiconductor die.

16 . The semiconductor device of claim 15 , further including a plurality of bumps electrically connecting the second semiconductor die to the interconnect structure.

17 . The semiconductor device of claim 15 , further including a third semiconductor die disposed over the second semiconductor die.

18 . The semiconductor device of claim 14 , further including a plurality of conductive vias formed through the first semiconductor die.

19 . The semiconductor device of claim 14 , further including a heat spreader or shielding layer formed over the first semiconductor die.

20 . The semiconductor device of claim 14 , wherein the interconnect structure includes:

a conductive layer; and

an insulating layer formed over the conductive layer.

21 . A semiconductor device, comprising:

a first semiconductor die;

an encapsulant deposited over the first semiconductor die; and

an interconnect structure formed over and partially through a first surface of the encapsulant, wherein the encapsulant includes a plurality of openings in a second surface of the encapsulant extending to the interconnect structure.

22 . The semiconductor device of claim 21 , further including a second semiconductor die disposed over the first semiconductor die.

23 . The semiconductor device of claim 23 , further including a third semiconductor die disposed over the second semiconductor die.

24 . The semiconductor device of claim 21 , further including a conductive layer disposed over the second surface of the encapsulant and into the openings and electrically connected to the interconnect structure.

25 . The semiconductor device of claim 21 , further including a plurality of conductive vias formed through the first semiconductor die.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED ON REEL 038378 FRAME 0418. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064908/0920 →
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053511/0298 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0418 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →