Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers
View Patent ↗A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die.
1. A semiconductor device, comprising:
a first semiconductor die;
a plurality of rounded bumps disposed proximate to the first semiconductor die;
a first conductive layer including a linear portion disposed over the first semiconductor die and non-linear portion disposed over the rounded bumps;
a second conductive layer including a non-linear portion disposed over a non-linear surface of the rounded bumps opposite the first conductive layer;
an encapsulant deposited around the first semiconductor die and rounded bumps; and
a plurality of first conductive vias formed through the encapsulant to electrically connect the linear portion of the first conductive layer to the first semiconductor die.
2. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die.
3. The semiconductor device of claim 2 , further including a plurality of second conductive vias formed through the encapsulant to electrically connect the second conductive layer to the second semiconductor die.
4. The semiconductor device of claim 2 , further including a plurality of second conductive vias formed through the first semiconductor die or second semiconductor die.
5. The semiconductor device of claim 1 , further including a plurality of stacked semiconductor devices electrically connected through the rounded bumps and first and second conductive layers.
6. A semiconductor device, comprising:
a first semiconductor die;
an interconnect structure disposed proximate to the first semiconductor die;
a first conductive layer including a linear portion disposed over the first semiconductor die and a non-linear portion disposed over a first non-linear surface of the interconnect structure;
a second conductive layer including a non-linear portion formed over a second non-linear surface of the interconnect structure opposite the first non-linear surface of the interconnect structure;
an encapsulant deposited around the first semiconductor die and interconnect structure; and
a first conductive via formed through the linear portion of the first conductive layer to the first semiconductor die.
7. The semiconductor device of claim 6 , wherein the second conductive layer includes a linear portion extending over the encapsulant.
8. The semiconductor device of claim 6 , further including a bump formed between the first conductive layer and the first semiconductor die.
9. The semiconductor device of claim 7 , further including a second semiconductor die disposed over the first semiconductor die.
10. The semiconductor device of claim 9 , further including a second conductive via formed through the encapsulant and the linear portion of the second conductive layer to electrically connect the second conductive layer to the second semiconductor die.
11. The semiconductor device of claim 7 , further including a second semiconductor die disposed over the first semiconductor die and including a similar footprint to the first semiconductor die.
12. The semiconductor device of claim 6 , wherein the interconnect structure includes a plurality of rounded bumps.
13. The semiconductor device of claim 6 , further including a plurality of stacked semiconductor devices electrically connected through the interconnect structure and first and second conductive layers.
14. The semiconductor device of claim 9 , further including an electrical interconnect disposed between the second conductive layer and second semiconductor die.
15. A semiconductor device, comprising:
a semiconductor die;
an interconnect structure including a non-linear surface disposed proximate to the semiconductor die;
a first conductive layer including a non-linear portion conformally disposed over a first portion of the non-linear surface of the interconnect structure and a linear portion extending over the semiconductor die;
a second conductive layer including a non-linear portion conformally disposed over a second portion of the non-linear surface of the interconnect structure opposite the first conductive layer; and
an encapsulant deposited around the semiconductor die and interconnect structure.
16. The semiconductor device of claim 15 , further including a conductive via formed through the first conductive layer to electrically connect the first conductive layer to the semiconductor die.
17. The semiconductor device of claim 15 , further including a second semiconductor die disposed over the semiconductor die.
18. The semiconductor device of claim 17 , further including a conductive via formed through the second conductive layer to electrically connect the second conductive layer to the second semiconductor die.
19. The semiconductor device of claim 17 , further including a plurality of bumps disposed within the encapsulant to electrically connect the semiconductor die to the second semiconductor die.
20. The semiconductor device of claim 15 , further including an electrical interconnect disposed between the semiconductor die and first conductive layer.
21. A semiconductor device comprising:
a semiconductor die;
an interconnect structure including a non-linear surface disposed proximate to the semiconductor die;
a conductive layer including a linear portion extending over the semiconductor die and a non-linear portion disposed over the non-linear surface of the interconnect structure;
a conductive via formed through the conductive layer and extending to the semiconductor die; and
a second conductive layer disposed over the non-linear surface of the interconnect structure opposite the conductive layer, wherein the second conductive layer includes a non-linear portion disposed over the non-linear surface of the interconnect structure.
22. The semiconductor device of claim 21 , further including a second semiconductor die disposed over the semiconductor die, wherein the second conductive layer extends over the second semiconductor die.
23. The semiconductor device of claim 22 , further including a second conductive via electrically connecting the second conductive layer to the second semiconductor die.
24. The semiconductor device of claim 22 , further including an electrical interconnect disposed between the second conductive layer and second semiconductor die.
25. A semiconductor device, comprising:
a first semiconductor die;
an interconnect structure including a non-linear surface disposed proximate to the first semiconductor die;
a first conductive layer including a non-linear portion disposed over the non-linear surface of the interconnect structure;
an encapsulant deposited around the first semiconductor die and interconnect structure, wherein the first conductive layer extends over the first semiconductor die; and
an electrical interconnect disposed between the first semiconductor die and a lateral surface of the first conductive layer over the first semiconductor die.
26. The semiconductor device of claim 25 , further including a second conductive layer disposed over the non-linear surface of the interconnect structure opposite the first conductive layer.
27. The semiconductor device of claim 26 , further including a second semiconductor die disposed over the first semiconductor die, wherein the second conductive layer extends over the second semiconductor die.
28. The semiconductor device of claim 27 , further including a second electrical interconnect disposed between the second conductive layer and second semiconductor die.