IP Library Granted Patent US 8,907,498
Granted Patent B2
US 8,907,498 · App. 13/691,440 · Granted Dec 9, 2014

Semiconductor device and method of forming a shielding layer between stacked semiconductor die

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Quick Facts
Patent No.
US 8,907,498
App. No.
13/691,440
Granted
Dec 9, 2014
Kind
B2
Abstract

A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.

Claims (43)

1. A semiconductor device, comprising:

a first semiconductor die;

an electromagnetic interference (EMI) shielding layer formed directly on a surface of the first semiconductor die;

a second semiconductor die disposed over the first semiconductor die and separated from the first semiconductor die by the EMI shielding layer;

an encapsulant deposited around the first semiconductor die and second semiconductor die; and

a first interconnect structure formed over the second semiconductor die and encapsulant.

2. The semiconductor device of claim 1 , further including a second interconnect structure formed over the first semiconductor die and encapsulant opposite the first interconnect structure.

3. The semiconductor device of claim 2 , further including a conductive pillar disposed between the first interconnect structure and second interconnect structure.

4. The semiconductor device of claim 1 , further including a bond wire formed between the EMI shielding layer and second interconnect structure.

5. The semiconductor device of claim 1 , further including a conductive via formed through the first semiconductor die.

6. The semiconductor device of claim 1 , further including a third semiconductor die disposed over the first interconnect structure or second interconnect structure.

7. A semiconductor device, comprising:

a first semiconductor die;

a second semiconductor die disposed over the first semiconductor die;

an electromagnetic interference (EMI) shielding layer disposed between the first semiconductor die and second semiconductor die;

a plurality of conductive pillars disposed around the first semiconductor die and second semiconductor die; and

an encapsulant deposited around the first semiconductor die, second semiconductor die, and conductive pillars.

8. The semiconductor device of claim 7 , further including a first interconnect structure formed over the second semiconductor die.

9. The semiconductor device of claim 8 , further including a second interconnect structure formed over the first semiconductor die opposite the first interconnect structure.

10. The semiconductor device of claim 9 , further including a bond wire formed between the EMI shielding layer and second interconnect structure.

11. The semiconductor device of claim 7 , further including a conductive via formed through the first semiconductor die.

12. A semiconductor device, comprising:

a first semiconductor die;

an electromagnetic interference (EMI) shielding layer formed over a surface of the first semiconductor die;

a second semiconductor die disposed over the first semiconductor die and separated from the first semiconductor die by the EMI shielding layer; and

a first interconnect structure formed over the second semiconductor die.

13. The semiconductor device of claim 12 , further including an encapsulant deposited around the first semiconductor die and second semiconductor die.

14. The semiconductor device of claim 12 , further including a second interconnect structure formed over the first semiconductor die opposite the first interconnect structure.

15. The semiconductor device of claim 14 , further including a conductive pillar disposed between the first interconnect structure and second interconnect structure.

16. The semiconductor device of claim 12 , further including a bond wire formed between the EMI shielding layer and second interconnect structure.

17. The semiconductor device of claim 12 , further including a conductive via formed through the first semiconductor die.

18. The semiconductor device of claim 12 , further including an insulating layer disposed between the first semiconductor die and second semiconductor die.

19. A semiconductor device, comprising:

a first semiconductor die;

an electromagnetic interference (EMI) shielding layer formed over a surface of the first semiconductor die;

a second semiconductor die disposed over the first semiconductor die and separated from the first semiconductor die by the EMI shielding layer; and

an encapsulant deposited around the first semiconductor die and second semiconductor die.

20. The semiconductor device of claim 19 , further including a first interconnect structure formed over the second semiconductor die.

21. The semiconductor device of claim 20 , further including a second interconnect structure formed over the first semiconductor die opposite the first interconnect structure.

22. The semiconductor device of claim 21 , further including a conductive pillar disposed between the first interconnect structure and second interconnect structure.

23. The semiconductor device of claim 21 , further including a bond wire formed between the EMI shielding layer and second interconnect structure.

24. The semiconductor device of claim 19 , further including a conductive via formed through the first semiconductor die.

25. The semiconductor device of claim 19 , further including an insulating layer disposed between the first semiconductor die and second semiconductor die.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF THE ASSIGNEE'S NAME ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0161. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064805/0735 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0161 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0352 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →