IP Library Granted Patent US 8,518,746
Granted Patent B2
US 8,518,746 · App. 12/874,787 · Granted Aug 27, 2013

Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,518,746
App. No.
12/874,787
Granted
Aug 27, 2013
Kind
B2
Abstract

A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die.

Claims (49)

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer including a plurality of conductive vias formed through the semiconductor wafer;

forming a cavity in the semiconductor wafer between the conductive vias;

disposing a plurality of semiconductor die within the cavity of the semiconductor wafer;

depositing an encapsulant within the cavity over the semiconductor die;

forming a first interconnect structure over a first surface of the semiconductor wafer; and

forming a second interconnect structure over a second surface of the semiconductor wafer opposite the first surface, the first and second interconnect structures being electrically connected to the conductive vias.

2. The method of claim 1 , wherein a coefficient of thermal expansion of the semiconductor wafer is similar to a coefficient of thermal expansion of the encapsulant.

3. The method of claim 1 , wherein a coefficient of thermal expansion of the semiconductor die is similar to a coefficient of thermal expansion of the encapsulant.

4. The method of claim 1 , further including disposing the semiconductor die in a stacked arrangement.

5. The method of claim 4 , further including disposing bumps between the stacked semiconductor die.

6. The method of claim 1 , further including disposing the semiconductor die in a side-by-side arrangement within the cavity of the semiconductor wafer.

7. The method of claim 1 , further including:

stacking a plurality of the semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first and second interconnect structures and conductive vias.

8. A method of making a semiconductor device, comprising:

providing a semiconductor wafer;

forming a first cavity in a first surface of the semiconductor wafer;

disposing a first semiconductor die within the first cavity of the semiconductor wafer;

depositing a first encapsulant within the first cavity;

forming a first interconnect structure over the first surface of the semiconductor wafer; and

forming a second interconnect structure over a second surface of the semiconductor wafer opposite the first surface of the semiconductor wafer.

9. The method of claim 8 , further including forming a plurality of conductive vias through the semiconductor wafer.

10. The method of claim 8 , wherein a coefficient of thermal expansion of the semiconductor wafer and coefficient of thermal expansion of the first semiconductor die are similar to a coefficient of thermal expansion of the first encapsulant.

11. The method of claim 8 , further including:

forming a second cavity in the second surface of the semiconductor wafer opposite the first surface of the semiconductor wafer;

disposing a second semiconductor die within the second cavity of the semiconductor wafer; and

depositing a second encapsulant within the second cavity.

12. The method of claim 8 , further including forming a plurality of conductive vias through the first semiconductor die.

13. The method of claim 8 , further including:

disposing a second semiconductor die over the first interconnect structure; and

depositing a second encapsulant over the second semiconductor die and first interconnect structure.

14. A method of making a semiconductor device, comprising:

providing a substrate including a plurality of first conductive vias formed through the substrate;

forming a first cavity in a first surface of the substrate;

disposing a first semiconductor die within the first cavity of the substrate;

depositing a first encapsulant within the first cavity; and

forming a first interconnect structure over the first surface of the substrate, the first interconnect structure being electrically connected to the first conductive vias.

15. The method of claim 14 , further including forming a second interconnect structure over a second surface of the substrate opposite the first surface of the substrate, the second interconnect structure being electrically connected to the first conductive vias.

16. The method of claim 14 , wherein a coefficient of thermal expansion of the substrate and coefficient of thermal expansion of the first semiconductor die are similar to a coefficient of thermal expansion of the first encapsulant.

17. The method of claim 14 , further including:

forming a second cavity in a second surface of the substrate opposite the first surface of the substrate;

disposing a second semiconductor die within the second cavity of the substrate; and

depositing a second encapsulant within the second cavity over the second semiconductor die.

18. The method of claim 14 , further including forming a plurality of second conductive vias through the first semiconductor die.

19. The method of claim 14 , further including disposing a second semiconductor die over the first semiconductor die.

20. The method of claim 14 , further including:

disposing a second semiconductor die over the first interconnect structure; and

depositing a second encapsulant over the second semiconductor die and first interconnect structure.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2010
From: PAGAILA, REZA A.; LIN, YAOJIAN; YOON, SEUNG UK
To: STATS CHIPPAC, LTD.
Reel/Frame 024932/0949 →