IP Library Granted Patent US 8,432,028
Granted Patent B2
US 8,432,028 · App. 13/053,096 · Granted Apr 30, 2013

Integrated circuit packaging system with package-on-package and method of manufacture thereof

Inventors: JinGwan Kim (Seoul, KR); KyuWon Lee (Ansung-Si, KR); MoonKi Jeong (Icheon-si, KR); SunYoung Chun (Suwon-Si, KR); JiHoon Oh (Suwon, KR)
Assignee: STATS ChipPAC Ltd.
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Quick Facts
Patent No.
US 8,432,028
App. No.
13/053,096
Granted
Apr 30, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base substrate top side; mounting a base integrated circuit over the base substrate top side, the base integrated circuit having an active side opposite an inactive side with the inactive side facing the base substrate top side; attaching a peripheral interconnect to the base substrate top side and a device peripheral pad of the base integrated circuit at the active side; mounting an interposer over the base integrated circuit and the peripheral interconnect, the interposer having an interposer top side and a window; and attaching a central interconnect to the interposer top side and a device central pad of the base integrated circuit at the active side, the central interconnect through the window.

Claims (51)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a base substrate having a base substrate top side;

mounting a base integrated circuit over the base substrate top side, the base integrated circuit having an active side opposite an inactive side with the inactive side facing the base substrate top side;

attaching a peripheral interconnect to the base substrate top side and a device peripheral pad of the base integrated circuit at the active side;

mounting an interposer over the base integrated circuit and the peripheral interconnect, the interposer having an interposer top side and a window; and

attaching a central interconnect to the interposer top side and a device central pad of the base integrated circuit at the active side, the central interconnect through the window.

2. The method as claimed in claim 1 further comprising forming a spacer directly on the active side, the spacer having a portion of the peripheral interconnect over the base integrated circuit therein.

3. The method as claimed in claim 1 further comprising forming a base encapsulation over the central interconnect and the peripheral interconnect.

4. The method as claimed in claim 1 further comprising forming a base encapsulation only covering a portion of the peripheral interconnect, the window, and an interposer interior pad of the interposer.

5. The method as claimed in claim 1 wherein mounting the interposer includes mounting the interposer over the base integrated circuit, the interposer having a length less than a length of the base substrate.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a base substrate having a base substrate bottom side and a base substrate top side;

mounting a base integrated circuit over the base substrate top side, the base integrated circuit having an active side opposite an inactive side with the inactive side facing the base substrate top side;

attaching a peripheral interconnect to the base substrate top side and a device peripheral pad of the base integrated circuit at the active side;

mounting an interposer over the base integrated circuit and the peripheral interconnect, the interposer having an interposer top side and a window;

attaching a central interconnect to the interposer top side and a device central pad of the base integrated circuit at the active side, the central interconnect through the window; and

attaching a base external interconnect to the base substrate bottom side.

7. The method as claimed in claim 6 further comprising:

forming a spacer directly on the active side, the spacer having a portion of the peripheral interconnect over the base integrated circuit therein; and

wherein:

mounting the interposer includes mounting the interposer directly on the spacer.

8. The method as claimed in claim 6 further comprising forming a base encapsulation over the central interconnect, and partially over the peripheral interconnect and the active side.

9. The method as claimed in claim 6 further comprising forming a base encapsulation only covering a portion of the peripheral interconnect, the window, and an interposer interior pad of the interposer, the base encapsulation exposing an interposer interconnect pad of the interposer.

10. The method as claimed in claim 6 wherein:

mounting the interposer includes mounting the interposer over the base integrated circuit, the interposer having an interposer external pad and a length less than a length of the base substrate; and

further comprising:

attaching a base connector to the base substrate top side and the interposer external pad.

11. An integrated circuit packaging system comprising:

a base substrate having a base substrate top side;

a base integrated circuit over the base substrate top side, the base integrated circuit having an active side opposite an inactive side with the inactive side facing the base substrate top side;

a peripheral interconnect attached to the base substrate top side and a device peripheral pad of the base integrated circuit at the active side;

an interposer over the base integrated circuit and the peripheral interconnect, the interposer having an interposer top side and a window; and

a central interconnect attached to the interposer top side and a device central pad of the base integrated circuit at the active side, the central interconnect through the window.

12. The system as claimed in claim 11 further comprising a spacer directly on the active side, the spacer having a portion of the peripheral interconnect over the base integrated circuit therein.

13. The system as claimed in claim 11 further comprising a base encapsulation over the central interconnect and the peripheral interconnect.

14. The system as claimed in claim 11 further comprising a base encapsulation only covering a portion of the peripheral interconnect, the window, and an interposer interior pad of the interposer.

15. The system as claimed in claim 11 wherein the interposer includes the interposer over the base integrated circuit, the interposer having a length less than a length of the base substrate.

16. The system as claimed in claim 11 wherein:

the base substrate includes a base substrate bottom side; and

further comprising:

a base external interconnect attached to the base substrate bottom side.

17. The system as claimed in claim 16 further comprising:

a spacer directly on the active side, the spacer having a portion of the peripheral interconnect over the base integrated circuit therein; and

wherein:

the interposer includes the interposer directly on the spacer.

18. The system as claimed in claim 16 further comprising a base encapsulation over the central interconnect and over a portion of the peripheral interconnect and the active side.

19. The system as claimed in claim 16 further comprising a base encapsulation only covering a portion of the peripheral interconnect, the window, and an interposer interior pad of the interposer, the base encapsulation exposing an interposer interconnect pad of the interposer.

20. The system as claimed in claim 16 wherein:

the interposer includes the interposer over the base integrated circuit, the interposer having an interposer external pad and a length less than a length of the base substrate; and

further comprising:

a base connector attached to the base substrate top side and the interposer external pad.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2011
From: KIM, JINGWAN; LEE, KYUWON; JEONG, MOONKI; CHUN, SUNYOUNG; OH, JIHOON
To: STATS CHIPPAC LTD.
Reel/Frame 026018/0091 →
Continuity (1)
Related Publication 20120241936A1 · Sep 27, 2012