IP Library Granted Patent US 8,476,775
Granted Patent B2
US 8,476,775 · App. 12/639,997 · Granted Jul 2, 2013

Integrated circuit packaging system with embedded interconnect and method of manufacture thereof

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Quick Facts
Patent No.
US 8,476,775
App. No.
12/639,997
Granted
Jul 2, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit with an adhesive attached thereto; connecting the integrated circuit and a plated interconnect pad; attaching an embedded interconnect to the plated interconnect pad; and forming an encapsulation, having an encapsulation first side and an encapsulation second side, around the integrated circuit, the embedded interconnect, and the plated interconnect pad with the embedded interconnect exposed from the encapsulation second side and the plated interconnect pad and the adhesive exposed from the encapsulation second side.

Claims (56)

1. An integrated circuit packaging system comprising:

an integrated circuit;

an adhesive attached to the integrated circuit;

a plated interconnect pad connected to the integrated circuit;

an embedded interconnect, having an elliptical shape, attached to the plated interconnect pad;

an internal interconnect connected between the integrated circuit and the plated interconnect pad, the internal interconnect in direct contact with no intervening element to the plated interconnect pad on the side of the plated interconnect pad attached to the embedded interconnect; and

an encapsulation, having an encapsulation first side and an encapsulation second side, around the integrated circuit, the embedded interconnect, and the plated interconnect pad with the embedded interconnect exposed from the encapsulation second side, the plated interconnect pad and the adhesive coplanar with the encapsulation first side and exposed from the encapsulation first side, and the elliptical shape of the embedded interconnects forming a mold interlock with the encapsulation.

2. The system as claimed in claim 1 further comprising a through interconnect covered by the encapsulation with the through interconnect exposed from and coplanar with the encapsulation first side as well as exposed from and coplanar with the encapsulation second side.

3. The system as claimed in claim 1 further comprising:

an interlock pad exposed at and coplanar with the encapsulation first side;

an interlock interconnect attached to the interlock pad; and

the interlock interconnect covered by the encapsulation with the interlock interconnect exposed from and coplanar with the encapsulation second side.

4. The system as claimed in claim 1 wherein the adhesive includes a thermal adhesive.

5. The system as claimed in claim 1 wherein the encapsulation around the embedded interconnect and the plated interconnect pad includes the mold interlock in the encapsulation.

6. The system as claimed in claim 1 further comprising an internal interconnect connecting the integrated circuit and a plated interconnect.

7. The system as claimed in claim 6 wherein:

the encapsulation first side is coplanar with the adhesive and the plated interconnect pad; and

the encapsulation second side is coplanar with the embedded interconnect.

8. The system as claimed in claim 6 further comprising:

a mountable structure with the encapsulation second side mounted over the mountable structure; and

a stackable integrated circuit-package mounted over the encapsulation first side.

9. The system as claimed in claim 6 wherein the internal interconnect includes a wire.

10. The system as claimed in claim 6 wherein the plated interconnect pad has the characteristics of a lead frame removed including an etched surface.

11. A method of manufacture of an integrated circuit packaging system comprising:

providing an integrated circuit with an adhesive attached thereto;

connecting the integrated circuit and a plated interconnect pad;

attaching an embedded interconnect, having an elliptical shape, to the plated interconnect pad;

connecting an internal interconnect between the integrated circuit and the plated interconnect pad, the internal interconnect in direct contact with no intervening element to the plated interconnect pad on the side of the plated interconnect pad attached to the embedded interconnect; and

forming an encapsulation, having an encapsulation first side and an encapsulation second side, around the integrated circuit, the embedded interconnect, and the plated interconnect pad with the embedded interconnect exposed from the encapsulation second side, the plated interconnect pad and the adhesive coplanar with the encapsulation first side and exposed from the encapsulation first side, and the elliptical shape of the embedded interconnect forming a mold interlock with the encapsulation.

12. The method as claimed in claim 11 further comprising:

forming the plated interconnect pad over a lead frame; and

removing selectively a portion of the lead frame.

13. The method as claimed in claim 11 wherein forming the encapsulation around the embedded interconnect and the plated interconnect pad includes forming the mold interlock in the encapsulation.

14. The method as claimed in claim 11 wherein providing the integrated circuit with the adhesive includes providing the integrated circuit with a thermal adhesive.

15. The method as claimed in claim 11 further comprising:

forming an interlock pad exposed at and coplanar with the encapsulation first side;

attaching an interlock interconnect to the interlock pad; and

wherein:

forming the encapsulation includes covering the interlock interconnect with the interlock interconnect exposed from and coplanar with the encapsulation second side.

16. A method of manufacture of an integrated circuit packaging system comprising:

providing an integrated circuit with an adhesive attached thereto;

connecting an internal interconnect between the integrated circuit and a plated interconnect pad with the plated interconnect pad adjacent to the integrated circuit;

attaching an embedded interconnect, having an elliptical shape, to the plated interconnect pad;

connecting an internal interconnect between the integrated circuit and the plated interconnect pad, the internal interconnect in direct contact with no intervening element to the plated interconnect pad on the side of the plated interconnect pad attached to the embedded interconnect; and

forming an encapsulation, having an encapsulation first side and an encapsulation second side, around the integrated circuit, the embedded interconnect, and the plated interconnect pad with the embedded interconnect exposed from the encapsulation second side, the plated interconnect pad and the adhesive coplanar with the encapsulation first side and exposed from the encapsulation first side, and the elliptical shape of the embedded interconnects forming a mold interlock with the encapsulation.

17. The method as claimed in claim 16 wherein forming the encapsulation includes:

forming the encapsulation first side coplanar with the adhesive and the plated interconnect pad; and

forming the encapsulation second side coplanar with the embedded interconnect.

18. The method as claimed in claim 16 further comprising:

forming a through interconnect; and

wherein:

forming the encapsulation includes covering the through interconnect with the through interconnect exposed from and coplanar with the encapsulation first side and exposed from and coplanar with the encapsulation second side.

19. The method as claimed in claim 16 further comprising:

mounting the encapsulation second side over a mountable structure with the embedded interconnect connected to the mountable structure; and

mounting a stackable integrated circuit package over the encapsulation first side with the plated interconnect pad connected to the stackable integrated circuit package.

20. The method as claimed in claim 16 wherein connecting the internal interconnect includes connecting a wire.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2009
From: YANG, JOUNGIN; CHO, YOUNGSIK; LEE, SUNGHYUN
To: STATS CHIPPAC LTD.
Reel/Frame 023689/0060 →