Integrated circuit packaging system with package-on-package and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, and forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed.
1. An integrated circuit packaging system comprising:
(a) a base integrated circuit package including:
a base substrate,
an exposed interconnect connected to the base substrate,
a base component over the base substrate,
a base encapsulation, and
(b) an encapsulation system including
a mold chase,
a buffer layer attachable to the mold chase, the buffer layer and the mold chase operable to engage the exposed interconnect,
wherein the exposed interconnect, partially exposed from the base encapsulation, exhibits physical features that are imprint images of that of the buffer layer and the mold chase.
2. The system as claimed in claim 1 wherein the buffer layer includes a soft material.
3. The system as claimed in claim 1 wherein the exposed interconnect includes the exposed interconnect on the base substrate and adjacent the base component, the base component partially exposed from the base encapsulation.
4. The system as claimed in claim 1 wherein the base integrated circuit package includes an interface module over the base substrate, the interface module having the exposed interconnect attached thereon.
5. The system as claimed in claim 1 wherein the base component includes the base component over the base substrate, the base component having the exposed interconnect attached thereto.
6. The system as claimed in claim 1 wherein
the buffer layer is operable to protect portions of the exposed interconnect when the buffer layer engages the exposed interconnect; and
the base encapsulation includes a recess in which a portion of the exposed interconnect is exposed, the recess exhibiting physical features that are imprint images of that of the buffer layer and the mold chase.
7. The system as claimed in claim 6 wherein the base encapsulation having characteristics of being formed by the encapsulation system with the buffer layer includes the encapsulation system with a film.
8. The system as claimed in claim 6 further comprising a stack integrated circuit package over the base integrated circuit package, the base integrated circuit package having an interface module over the base component and with the exposed interconnect attached thereon.
9. The system as claimed in claim 6 further comprising a stack integrated circuit package over the base integrated circuit package, whereby the base integrated circuit package having the base component includes a redistribution layer die with the exposed interconnect attached thereon.