IP Library Granted Patent US 8,501,618
Granted Patent B2
US 8,501,618 · App. 13/181,290 · Granted Aug 6, 2013

Semiconductor device and method of forming RDL wider than contact pad along first axis and narrower than contact pad along second axis

Inventors: Yaojian Lin (Singapore, SG); Xia Feng (Singapore, SG); Jianmin Fang (Singapore, SG); Kang Chen (Singapore, SG)
Assignee: STATS ChipPAC, Ltd.
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Quick Facts
Patent No.
US 8,501,618
App. No.
13/181,290
Granted
Aug 6, 2013
Kind
B2
Abstract

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Claims (47)

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first conductive layer over a surface of the semiconductor die;

forming a first insulating layer over the surface of the semiconductor die;

forming a second insulating layer over the first insulating layer and first conductive layer;

forming an opening in the second insulating layer over the first conductive layer, the opening extending beyond the first conductive layer over first and second opposing edges of the first conductive layer while the second insulating layer overlies the first conductive layer with respect to third and fourth opposing edges of the first conductive layer perpendicular to the first and second opposing edges of the first conductive layer;

forming a second conductive layer over the first and second insulating layers and over a portion of the first conductive layer within the opening in the second insulating layer; and

forming a third insulating layer over the second conductive layer and first and second insulating layers.

2. The method of claim 1 , wherein the opening in the second insulating layer extends beyond the first and second opposing edges of the first conductive layer by 10-20 micrometers.

3. The method of claim 1 , wherein the second insulating layer overlies the first conductive layer with respect to the third and fourth opposing edges of the first conductive layer by 10-20 micrometers.

4. The method of claim 1 , wherein a width of the second conductive layer is greater than a width of the first conductive layer between the first and second opposing edges of the first conductive layer, and a width of the second conductive layer is less than a width of the first conductive layer between the third and fourth opposing edges of the first conductive layer.

5. The method of claim 1 , wherein a width of a contact interface between the first conductive layer and second conductive layer ranges from 20-40 micrometers.

6. The method of claim 1 , wherein a pitch of the first conductive layer ranges from 30-50 micrometers.

7. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first conductive layer over a surface of the semiconductor die;

forming a first insulating layer including an opening over the first conductive layer;

forming a second conductive layer within the opening over the first conductive layer, the second conductive layer including a width that is less than a width of the first conductive layer along a first axis and a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis; and

forming a second insulating layer over the second conductive layer and first insulating layer.

8. The method of claim 7 , further including forming the opening in the first insulating layer extending beyond the first conductive layer over first and second opposing edges of the first conductive layer while the second insulating layer overlies the first conductive layer with respect to third and fourth opposing edges of the first conductive layer perpendicular to the first and second opposing edges of the first conductive layer.

9. The method of claim 7 , further including forming a third insulating layer over the surface of the semiconductor die prior to forming the first insulating layer.

10. The method of claim 7 , wherein the width of the second conductive layer is greater than the width of the first conductive layer along the second axis by 10-20 micrometers.

11. The method of claim 7 , wherein the width of the first conductive layer is greater than the width of the second conductive layer along the first axis by 10-20 micrometers.

12. The method of claim 7 , wherein a width of a contact interface between the first conductive layer and second conductive layer ranges from 20-40 micrometers.

13. The method of claim 7 , wherein a pitch of the first conductive layer ranges from 30-50 micrometers.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first conductive layer over a surface of the semiconductor die;

forming a first insulating layer over the semiconductor die; and

forming a second conductive layer over the first conductive layer that is wider than the first conductive layer along a first axis and narrower than the first conductive layer along a second axis perpendicular to the first axis.

15. The method of claim 14 , further including:

forming a second insulating layer over the surface of the semiconductor die prior to forming the first insulating layer; and

forming a third insulating layer over the second conductive layer and first insulating layer.

16. The method of claim 14 , further including forming an opening in the first insulating layer over the first conductive layer, the opening extending beyond the first conductive layer on first and second opposing edges of the first conductive layer while the first insulating layer overlies the first conductive layer with respect to third and fourth opposing edges of the first conductive layer perpendicular to the first and second opposing edges of the first conductive layer.

17. The method of claim 14 , wherein a width of the second conductive layer is greater than a width of the first conductive layer along the first axis by 10-20 micrometers.

18. The method of claim 14 , wherein a width of the second conductive layer is less than a width of the first conductive layer along the second axis by 10-20 micrometers.

19. The method of claim 14 , wherein a width of a contact interface between the first conductive layer and second conductive layer ranges from 20-40 micrometers.

20. The method of claim 14 , wherein a pitch of the first conductive layer ranges from 30-50 micrometers.

21. A semiconductor device, comprising:

a semiconductor die;

a first conductive layer formed over a surface of the semiconductor die;

a first insulating layer formed over the surface of the semiconductor die; and

a second conductive layer formed over the first conductive layer that is wider than the first conductive layer along a first axis and narrower than the first conductive layer along a second axis perpendicular to the first axis.

22. The semiconductor device of claim 21 , wherein a width of the second conductive layer is greater than a width of the first conductive layer along the first axis by 10-20 micrometers.

23. The semiconductor device of claim 21 , wherein a width of the second conductive layer is less than a width of the first conductive layer along the second axis by 10-20 micrometers.

24. The semiconductor device of claim 21 , wherein a width of a contact interface between the first conductive layer and second conductive layer ranges from 20-40 micrometers.

25. The semiconductor device of claim 21 , wherein a pitch of the first conductive layer ranges from 30-50 micrometers.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2011
From: LIN, YAOJIAN; FENG, XIA; CHEN, KANG; FANG, JIANMIN
To: STATS CHIPPAC, LTD.
Reel/Frame 026580/0523 →
Continuity (2)
Provisional Application 61367807 · Jul 26, 2010
Related Publication 20120018904A1 · Jan 26, 2012