IP Library Granted Patent US 8,455,993
Granted Patent B2
US 8,455,993 · App. 12/789,077 · Granted Jun 4, 2013

Integrated circuit packaging system with multiple row leads and method of manufacture thereof

Inventors: Zigmund Ramirez Camacho (Singapore, SG); Henry Descalzo Bathan (Singapore, SG); Emmanuel Espiritu (Singapore, SG)
Assignee: STATS ChipPAC Ltd.
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Quick Facts
Patent No.
US 8,455,993
App. No.
12/789,077
Granted
Jun 4, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a first lead adjacent and staggered to a second lead, the first lead having a first external connection portion with a first external conductive layer and a first internal connection portion, the first external connection portion oriented laterally outwards from the first internal connection portion, and the second lead having a second external connection portion with a second external conductive layer and a second internal connection portion; connecting an integrated circuit device with the first internal connection portion and with the second internal connection portion; forming an encapsulation over the integrated circuit device with the first lead and the second lead exposed; and forming a solder mask on the encapsulation, on the first lead, and on the second lead with the first external conductive layer and the second external conductive layer exposed from the solder mask.

Claims (56)

1. A method of manufacture of an integrated circuit packaging system comprising:

forming a first lead adjacent and staggered to a second lead,

the first lead having a first external connection portion with a first external conductive layer and a first internal connection portion, the first external connection portion oriented laterally outwards from the first internal connection portion, and

the second lead having a second external connection portion with a second external conductive layer and a second internal connection portion;

forming a third lead adjacent to the first internal connection portion and the second internal connection portion along adjacent sides of the third lead;

connecting an integrated circuit device with the first internal connection portion, with the third lead, and with the second internal connection portion;

forming an encapsulation over the integrated circuit device with the first lead, the second lead, the third lead, the first external connection portion, and the second external connection portion exposed; and

forming a solder mask on the encapsulation, on the first lead, and on the second lead with the first external conductive layer and the second external conductive layer exposed from the solder mask.

2. The method as claimed in claim 1 wherein forming the first lead includes forming the second external connection portion having a second external width at least twice a second internal width of the second internal connection portion.

3. The method as claimed in claim 1 wherein forming the first lead includes the forming the second external connection portion oriented laterally outwards from the second internal connection portion.

4. The method as claimed in claim 1 further comprising:

forming a die pad; and

wherein:

forming the first internal connection portion and the second internal connection portion includes forming the first internal connection portion and the second internal connection portion equidistant from the die pad.

5. The method as claimed in claim 1 further comprising:

forming a die pad; and

wherein:

forming the first lead includes forming a third lead between the second lead and the die pad.

6. A method of manufacture of an integrated circuit packaging system comprising:

forming a first lead adjacent and staggered to a second lead,

the first lead having a first external connection portion with a first external conductive layer and a first internal connection portion, the first external connection portion oriented laterally outwards from the first internal connection portion and having a first external width at least twice a first internal width of the first internal connection portion, and

the second lead having a second external connection portion with a second external conductive layer and a second internal connection portion;

forming a third lead adjacent to the first internal connection portion and the second internal connection portion along adjacent sides of the third lead;

connecting an integrated circuit device with the first internal connection portion, with the third lead, and with the second internal connection portion;

forming an encapsulation over the integrated circuit device with the first external connection portion and the second external connection portion exposed from the encapsulation; and

forming a solder mask on the encapsulation, on the first lead, and on the second lead with the first external conductive layer and the second external conductive layer exposed from the solder mask.

7. The method as claimed in claim 6 wherein:

forming the first lead adjacent and staggered to the second lead includes forming the second lead having the second internal connection portion covered with a second internal conductive layer; and

connecting the integrated circuit device includes connecting the integrated circuit device with the second internal conductive layer.

8. The method as claimed in claim 6 wherein:

forming the first lead includes forming the first lead having the first internal connection portion covered with a first internal conductive layer; and

connecting the integrated circuit device includes connecting the integrated circuit device with the first internal conductive layer.

9. The method as claimed in claim 6 wherein forming the first lead includes forming a third lead having a third external width equal to the first external width of the first lead.

10. An integrated circuit packaging system comprising:

a first lead having a first external connection portion with a first external conductive layer and a first internal connection portion, the first external connection portion oriented laterally outwards from the first internal connection portion;

a second lead formed adjacent and staggered to the first lead, the second lead having a second external connection portion with a second external conductive layer and a second internal connection portion;

a third lead formed adjacent to the first internal connection portion and the second internal connection portion along adjacent sides of the third lead;

an integrated circuit device connected with the first internal connection portion, with the third lead, and with the second internal connection portion;

an encapsulation formed over the integrated circuit device with the first lead and the second lead exposed, the first external connection portion and the second external connection portion exposed from the encapsulation; and

a solder mask formed on the encapsulation, on the first lead, and on the second lead with the first external conductive layer and the second external conductive layer exposed from the solder mask.

11. The system as claimed in claim 10 wherein the second external connection portion has a second external width at least twice a second internal width of the second internal connection portion.

12. The system as claimed in claim 10 wherein the second external connection portion includes the second external connection portion oriented laterally outwards from the second internal connection portion.

13. The system as claimed in claim 10 further comprising:

a die pad; and

wherein:

the first internal connection portion and the second internal connection portion includes the first internal connection portion and the second internal connection portion are equidistant from the die pad.

14. The system as claimed in claim 10 further comprising:

a die pad; and

a third lead between the second lead and the die pad.

15. The system as claimed in claim 10 wherein:

the second lead includes a second internal conductive layer covering the second internal connection portion; and

the integrated circuit device is connected to the second internal conductive layer.

16. The system as claimed in claim 10 wherein:

the first lead includes a first internal conductive layer covering the first internal connection portion; and

the integrated circuit device is connected to the first internal conductive layer.

17. The system as claimed in claim 10 further comprising a third lead having a third external width equal to the first external width of the first lead.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: CAMACHO, ZIGMUND RAMIREZ; BATHAN, HENRY DESCALZO; ESPIRITU, EMMANUEL
To: STATS CHIPPAC LTD.
Reel/Frame 024540/0616 →
Continuity (1)
Related Publication 20110291251A1 · Dec 1, 2011