IP Library Granted Patent US 8,460,968
Granted Patent B2
US 8,460,968 · App. 12/885,137 · Granted Jun 11, 2013

Integrated circuit packaging system with post and method of manufacture thereof

Inventors: DongSam Park (Seongnam-si, KR); HanGil Shin (Seongnam-si, KR); HeeJo Chi (Ichon-si, KR)
Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 8,460,968
App. No.
12/885,137
Granted
Jun 11, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a stack substrate with a component side; connecting an integrated circuit component to the component side; attaching a conductive post to the component side and adjacent the integrated circuit component, the conductive post having a protruded end above the integrated circuit component; forming a protection layer on a top and sides of the protruded end, the protection layer having a width equal to a width of the conductive post; applying a stack encapsulation over the integrated circuit component, over the stack substrate, and around a portion of the conductive post, the protection layer exposed from the stack encapsulation; and mounting a base package under the stack substrate, base package connected to the stack substrate.

Claims (39)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a stack substrate with a component side;

connecting an integrated circuit component to the component side;

attaching a conductive post to the component side and adjacent the integrated circuit component, the conductive post having a protruded end above the integrated circuit component;

forming a protection layer on a top and sides of the protruded end, the protection layer having a width equal to a width of the conductive post;

applying a stack encapsulation over the integrated circuit component, over the stack substrate, and around a portion of the conductive post, the protection layer exposed from the stack encapsulation; and

mounting a base package under the stack substrate, base package connected to the stack substrate.

2. The method as claimed in claim 1 further comprising applying a package encapsulation around a portion of the protruded end with the protection layer exposed above the package encapsulation.

3. The method as claimed in claim 1 further comprising attaching a chip to the protection layer over the stack package.

4. The method as claimed in claim 1 further comprising attaching an electronic component to a side of the stack substrate opposite the component side.

5. The method as claimed in claim 1 further comprising forming a redistribution metal layer on the stack package, the redistribution metal layer connected to the protruded end.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a stack substrate with a component side;

connecting an integrated circuit component to the component side;

attaching a conductive post to the component side and adjacent the integrated circuit component, the conductive post having a protruded end above the integrated circuit component;

forming a protection layer on the protruded end, the protection layer having a width equal to a width of the conductive post;

applying a stack encapsulation over the integrated circuit component, over the stack substrate, and around a portion of the conductive post, the protection layer exposed from the stack encapsulation;

mounting a base package under the stack substrate, base package connected to the stack substrate; and

applying a package encapsulation over at least a portion of the stack package and between the stack package and the base package.

7. The method as claimed in claim 6 wherein applying the package encapsulation includes forming a cavity in the encapsulation to expose a portion of the stack substrate opposite the component side.

8. The method as claimed in claim 6 wherein applying the stack encapsulation includes forming the stack encapsulation having a raised platform area, the raised platform area connected to the protection layer and partially exposed from the package encapsulation.

9. The method as claimed in claim 6 further comprising attaching a package connector to a side of the stack substrate opposite the component side, the package connector partially exposed from the package encapsulation.

10. The method as claimed in claim 6 further comprising forming a redistribution metal layer on the stack package, the redistribution metal layer connected to the protruded end and exposed from the package encapsulation.

11. An integrated circuit packaging system comprising:

a stack substrate with a component side;

an integrated circuit component connected to the component side;

a conductive post connected to the component side and adjacent the integrated circuit component, the conductive post having a protruded end above the integrated circuit component;

a protection layer on the protruded end, the protection layer having a width equal to a width of the conductive post;

a stack encapsulation over the integrated circuit component, over the stack substrate, and around a portion of the conductive post, the protection layer exposed from the stack encapsulation; and

a base package under the stack substrate, the base package connected to the stack substrate.

12. The system as claimed in claim 11 further comprising a package encapsulation around a portion of the protruded end with the protection layer exposed above the package encapsulation.

13. The system as claimed in claim 11 further comprising a chip attached to the protection layer over the stack package.

14. The system as claimed in claim 11 further comprising an electronic component attached to a side of the stack substrate opposite the component side.

15. The system as claimed in claim 11 further comprising a redistribution metal layer on the stack package, the redistribution metal layer connected to the protruded end.

16. The system as claimed in claim 11 further comprising a package encapsulation over at least a portion of the stack package and between the stack package and the base package.

17. The system as claimed in claim 16 wherein the package encapsulation includes a cavity in the encapsulation to expose a portion of the stack substrate opposite the component side.

18. The system as claimed in claim 16 wherein the stack encapsulation includes the stack encapsulation having a raised platform area, the raised platform area connected to the protection layer and partially exposed from the package encapsulation.

19. The system as claimed in claim 16 further comprising a package connector attached to a side of the stack substrate opposite the component side, the package connector partially exposed from the package encapsulation.

20. The system as claimed in claim 16 further comprising a redistribution metal layer on the stack package, the redistribution metal layer connected to the protruded end and exposed from the package encapsulation.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2010
From: PARK, DONGSAM; SHIN, HANGIL; CHI, HEEJO
To: STATS CHIPPAC LTD.
Reel/Frame 025030/0744 →
Continuity (1)
Related Publication 20120068332A1 · Mar 22, 2012