Integrated circuit package system with warp-free chip
An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer.
1. An integrated circuit package system comprising:
a semiconductor chip;
a stress-relieving layer on the semiconductor chip;
an adhesion layer on the stress relieving layer;
electrical interconnects bonded to the adhesion layer; and
an additional stress-relieving layer on the adhesion layer and attached between the electrical interconnects.
2. The system as claimed in claim 1 wherein:
the adhesion layer is on selected regions of the stress-relieving layer adjacent the diced sides of the semiconductor chip; and
the semiconductor chip is mounted by the adhesion layer on the electrical interconnects.
3. The system as claimed in claim 1 wherein:
the adhesion layer is thicker than the stress-relieving layer; and
the adhesion layer on the electrical interconnects and over the sides thereof.
4. The system as claimed in claim 1 wherein:
the additional stress-relieving layer holds the semiconductor chip over the electrical interconnects.
5. The system as claimed in claim 1 further comprising:
bond wires electrically connecting the semiconductor chip to the electrical interconnects; and
an encapsulant encapsulating the semiconductor chip, the bond wires, and the electrical interconnects.
6. The system as claimed in claim 1 wherein:
the stress-relieving layer is a low modulus stress-relieving layer;
the adhesion layer is a high modulus adhesion layer;
the low modulus stress-relieving layer and the high modulus adhesion layer are fully cured; and
the electrical interconnects are leadfingers.
7. The system as claimed in claim 6 wherein:
the high modulus adhesion layer is on selected regions of the low modulus stress-relieving layer adjacent the diced sides of the semiconductor chip; and
the semiconductor chip is mounted by the high modulus adhesion layer on the leadfingers.
8. The system as claimed in claim 6 wherein:
the high modulus adhesion layer is thicker than the low modulus stress-relieving layer; and
the high modulus adhesion layer on the leadfingers and over the sides thereof.
9. The system as claimed in claim 6 wherein:
the additional stress-relieving layer holds the semiconductor chip on the leadfingers.
10. The system as claimed in claim 6 further comprising:
bond wires electrically connecting the semiconductor chip to the leadfingers; and
an encapsulant encapsulating the semiconductor chip, the bond wires, and the leadfingers.