Semiconductor packaging system with an aligned interconnect and method of manufacture thereof
View Patent ↗A method of manufacture of a semiconductor packaging system includes: providing a base substrate having edges; mounting an electrical interconnect on the base substrate; and applying an encapsulant having a reference marker and an opening over the electrical interconnect, the reference marker around the electrical interconnect based on physical locations of the edges.
1. A method of manufacture of a semiconductor packaging system comprising:
providing a base substrate having edges;
mounting an electrical interconnect on the base substrate;
applying an encapsulant, having reference markers, over the electrical interconnect, the reference markers triangulated to a central axis of the electrical interconnect based on physical locations of the edges; and
forming a hole, having a central axis, in the encapsulant, the central axis of the hole coincident with the central axis of the electrical interconnect, the electrical interconnect in the hole and exposed below non-horizontal sides of the hole.
2. The method as claimed in claim 1 wherein applying the encapsulant includes forming the reference markers in the encapsulant.
3. The method as claimed in claim 1 wherein applying the encapsulant includes removing a portion of the encapsulant to expose the electrical interconnect.
4. The method as claimed in claim 1 wherein:
providing the base substrate includes providing the base substrate having an assembly hole between the edges and the encapsulant; and
applying the encapsulant includes forming the reference markers in the encapsulant based on a physical location of the assembly hole.
5. The method as claimed in claim 1 further comprising:
mounting an integrated circuit device on the base substrate; and
connecting a system connector to the base substrate.
6. A method of manufacture of a semiconductor packaging system comprising:
providing a base substrate having edges and strip edge patterns on the edges;
mounting an electrical interconnect on the base substrate;
applying an encapsulant, having reference markers, over the electrical interconnect, the reference markers triangulated to a central axis of the electrical interconnect and based on physical locations of the strip edge patterns; and
forming a hole, having a central axis, in the encapsulant, the central axis of the hole coincident with the central axis of the electrical interconnect, the electrical interconnect in the hole and exposed below non-horizontal sides of the hole.
7. The method as claimed in claim 6 wherein applying the encapsulant includes forming the reference markers into a portion of the encapsulant.
8. The method as claimed in claim 6 wherein applying the encapsulant includes laser ablating a portion of the encapsulant having a central axis of the hole coincident with a central axis of the electrical interconnect.
9. The method as claimed in claim 6 wherein:
providing the base substrate includes providing the base substrate having an assembly hole between the edges and the encapsulant; and
applying the encapsulant includes forming the reference markers in the encapsulant based on a physical location of the assembly hole and the strip edge patterns.
10. The method as claimed in claim 6 further comprising:
mounting an integrated circuit device on the base substrate and covered by the encapsulant; and
connecting a system connector to the base substrate, the system connector on a side of the base substrate facing away from the integrated circuit device.
11. A semiconductor packaging system comprising:
a base substrate having edges;
an electrical interconnect mounted to the base substrate; and
an encapsulant having reference markers and a hole, the electrical interconnect in the hole and exposed below non-horizontal sides of the hole, a central axis 120 of the hole coincident with a central axis of the electrical interconnect having a physical location triangulated by the reference markers based on physical locations of the edges.
12. The system as claimed in claim 11 wherein the encapsulant includes the reference markers formed in the encapsulant.
13. The system as claimed in claim 11 wherein the encapsulant includes a portion of the encapsulant removed to expose the electrical interconnect.
14. The system as claimed in claim 11 wherein:
the base substrate having an assembly hole between the edges and the encapsulant; and
the encapsulant includes the reference markers formed in the encapsulant based on a physical location of the assembly hole.
15. The system as claimed in claim 11 further comprising:
an integrated circuit device mounted on the base substrate; and
a system connector connected to the base substrate.
16. The system as claimed in claim 11 wherein:
the base substrate having strip edge patterns on the edges; and
the encapsulant includes the reference markers based on physical locations of the strip edge patterns.
17. The system as claimed in claim 16 wherein the encapsulant includes the reference markers formed into a portion of the encapsulant.
18. The system as claimed in claim 16 wherein the encapsulant includes a central axis of the hole coincident with a central axis of the electrical interconnect.
19. The system as claimed in claim 16 wherein:
the base substrate having an assembly hole between the edges and the encapsulant; and
the encapsulant includes the reference markers formed in the encapsulant based on a physical location of the assembly hole and the strip edge patterns.
20. The system as claimed in claim 16 further comprising:
an integrated circuit device mounted on the base substrate and covered by the encapsulant; and
a system connector connected to the base substrate, the system connector on a side of the base substrate facing away from the integrated circuit device.