IP Library Granted Patent US 8,513,542
Granted Patent B2
US 8,513,542 · App. 11/276,645 · Granted Aug 20, 2013

Integrated circuit leaded stacked package system

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Quick Facts
Patent No.
US 8,513,542
App. No.
11/276,645
Granted
Aug 20, 2013
Kind
B2
Abstract

An integrated circuit leaded stacked package system includes forming a no-lead integrated circuit package having a mold cap, and attaching a mold cap of an extended-lead integrated circuit package facing the mold cap of the no-lead integrated circuit package.

Claims (23)

1. An integrated circuit leaded stacked package system comprising:

forming a no-lead integrated circuit package having a mold cap;

attaching a mold cap of an extended-lead integrated circuit package having extended leads with a stack portion opposite a base portion, the mold cap of the extended-lead integrated circuit package facing the mold cap of the no-lead integrated circuit package, the base portion thereunder; and

attaching a top integrated circuit package with exposed leads on the stack portion of the extended leads having the base portion horizontally extended away from the exposed leads and the extended-lead integrated circuit package.

2. The system as claimed in claim 1 wherein attaching the top integrated circuit package includes attaching the top integrated circuit package on the extended-lead integrated circuit package having second leads.

3. The system as claimed in claim 1 wherein attaching the extended-lead integrated circuit package comprises applying a lead-end encapsulant over the lead ends of the extended leads.

4. The system as claimed in claim 1 wherein attaching the extended-lead integrated circuit package comprises applying a package encapsulant over a portion of the no-lead integrated circuit package and a portion of the extended-lead integrated circuit package including lead ends of the extended leads.

5. An integrated circuit leaded stacked package system comprising:

a no-lead integrated circuit package having a mold cap;

a mold cap of an extended-lead integrated circuit package having extended leads with a stack portion opposite a base portion, the mold cap of the extended-lead integrated circuit package facing the mold cap of the no-lead integrated circuit package, the base portion thereunder; and

a top integrated circuit package with exposed leads on the stack portion of the extended leads having the base portion horizontally extended away from the exposed leads and the extended-lead integrated circuit package.

6. The system as claimed in claim 5 wherein the extended-lead integrated circuit package includes the extended-lead integrated circuit package having second leads.

7. The system as claimed in claim 5 wherein the extended-lead integrated circuit package comprises a lead-end encapsulant over the lead ends of the extended leads.

8. The system as claimed in claim 5 wherein the extended-lead integrated circuit package comprises a package encapsulant over a portion of the no-lead integrated circuit package and a portion of the extended-lead integrated circuit package including lead ends of the extended leads.

9. The system as claimed in claim 5 wherein:

the no-lead integrated circuit package is a no-lead integrated circuit package having a no-lead pad;

the extended-lead integrated circuit package is an extended-lead integrated circuit package with an extended lead having an extension beyond a mold cap; and

further comprising:

an extended-lead integrated circuit package with a lead end of the extended lead substantially coplanar with the no-lead pad.

10. The system as claimed in claim 9 wherein the extended-lead integrated circuit package comprises extended leads formed towards a side having a first integrated circuit die.

11. The system as claimed in claim 9 wherein the extended-lead integrated circuit package comprises an interposer surface of the extended-lead integrated circuit package.

12. The system as claimed in claim 9 wherein the extended-lead integrated circuit package comprises an encapsulant with an interposer surface of the extended-lead integrated circuit package substantially exposed.

13. The system as claimed in claim 9 wherein the extended-lead integrated circuit package is an interposer.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2006
From: KUAN, HEAP HOE; HO, TSZ YIN; MERILO, DIOSCORO A.; CHOW, SENG GUAN; DIMAANO, JR., ANTONIO B.
To: STATS CHIPPAC LTD.
Reel/Frame 017282/0792 →