IP Library Granted Patent US 8,466,567
Granted Patent B2
US 8,466,567 · App. 12/884,134 · Granted Jun 18, 2013

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

Inventors: DaeSik Choi (Seoul, KR); SangMi Park (Pucheon Si, KR); Oh Han Kim (Ichon-si, KR)
Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 8,466,567
App. No.
12/884,134
Granted
Jun 18, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Claims (28)

1. An integrated circuit packaging system comprising:

base device pads having device pad surfaces coplanar to each other characteristic of being formed on a carrier top side of a connection carrier;

base interconnected pads having interconnect pad surfaces coplanar to each other characteristic of being formed on the carrier top side;

a base integrated circuit connected to the base device pads;

base vertical interconnects directly on the base interconnect pads;

a base package substrate attached to the base integrated circuit and directly on the base vertical interconnects;

a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads, the base encapsulation partially exposing the base device pads and the base interconnect pads opposite the base package substrate; and

base external interconnects attached to a base substrate bottom side of the base package substrate, wherein the base encapsulation includes a step portion over the base integrated circuit, the base encapsulation partially exposing the base device pads at the step portion.

2. The system as claimed in claim 1 further comprising base device connectors connected to the base integrated circuit and the base device pads.

3. The system as claimed in claim 1 further comprising conductive traces connected to the base device pads and the base interconnect pads.

4. The system as claimed in claim 1 wherein the base interconnect pads surround the base device pads.

5. The system as claimed in claim 1 wherein the base encapsulation includes an external planar surface of the base encapsulation coplanar with device pad surfaces of the base device pads and interconnect pad surfaces of the base interconnect pads.

6. The system as claimed in claim 1 further comprising a base component connected to the base package substrate and attached to the base integrated circuit.

7. An integrated circuit packaging system comprising:

base device pads having device pad surfaces coplanar to each other characteristic of being formed on a carrier top side of a connection carrier;

base interconnect pads having interconnect pad surfaces coplanar to each other characteristic of being formed on the carrier top side;

a base integrated circuit connected to the base device pads;

base vertical interconnects mounted directly on the base interconnect pads;

a base package substrate attached to the base integrated circuit and directly on the base vertical interconnects;

a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads, the base encapsulation partially exposing the base device pads and the base interconnect pads opposite the base package substrate; and

base external interconnects attached to a base substrate bottom side of the base package substrate, wherein the base encapsulation includes a recess over the base integrated circuit, the base encapsulation partially exposing the base device pads within the recess.

8. The system as claimed in claim 1 further comprising a stack component connected to the base device pads.

9. The system as claimed in claim 7 further comprising base device connectors connected to the base integrated circuit and the base device pads.

10. The system as claimed in claim 7 further comprising conductive traces connected to the base device pads and the base interconnect pads.

11. The system as claimed in claim 7 wherein the base interconnect pads surround the base device pads.

12. The system as claimed in claim 7 wherein the base encapsulation includes an external planar surface of the base encapsulation coplanar with device pad surfaces of the base device pads and interconnect pad surfaces of the base interconnect pads.

13. The system as claimed in claim 7 further comprising a base component connected to the base package substrate and attached to the base integrated circuit.

14. The system as claimed in claim 7 further comprising a stack component connected to the base device pads.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2010
From: CHOI, DAESIK; PARK, SANGMI; KIM, OH HAN
To: STATS CHIPPAC LTD.
Reel/Frame 025030/0325 →
Continuity (1)
Related Publication 20120068319A1 · Mar 22, 2012