IP Library Granted Patent US 8,409,979
Granted Patent B2
US 8,409,979 · App. 13/149,669 · Granted Apr 2, 2013

Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties

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Quick Facts
Patent No.
US 8,409,979
App. No.
13/149,669
Granted
Apr 2, 2013
Kind
B2
Abstract

A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.

Claims (67)

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first insulating layer including a plurality of openings disposed over the substrate;

forming a plurality of conductive pads within the openings of the first insulating layer over the substrate;

forming a plurality of recesses partially into the conductive pads while retaining a portion of the conductive pads under the recesses by,

(a) forming a second insulating layer including a plurality of openings disposed over the conductive pads, and

(b) forming the plurality of recesses through a surface of the conductive pads within the openings of the second insulating layer, the recesses each including a sidewall extending to a surface of the recess to expand an interconnect surface area of the conductive pads;

providing a semiconductor die including a plurality of bumps formed over a surface of the semiconductor die; and

disposing the semiconductor die over the substrate with the bumps contacting the expanded interconnect surface area of the conductive pads to increase bonding strength of the bumps to the conductive pads.

2. The method of claim 1 , further including:

forming a first conductive layer over the substrate;

forming a third insulating layer over the first insulating layer including plurality of openings in the third insulating layer disposed over the first conductive layer; and

forming the conductive pads over the first conductive layer within the openings of the third insulating layer.

3. The method of claim 2 , further including:

forming a second conductive layer over the substrate; and

removing a portion of the first insulating layer by laser direct ablation to expose the second conductive layer.

4. The method of claim 1 , further including arranging the recesses as concentric rings, circular recesses, or parallel linear trenches.

5. The method of claim 1 , further including depositing a mold underfill material between the semiconductor die and substrate.

6. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first insulating layer over the substrate;

forming a plurality of first conductive pads over the substrate;

expanding an interconnect surface area of the first conductive pads by forming a plurality of recesses partially into the first conductive pads while retaining a portion of the first conductive pads under the recesses to expand an interconnect surface area of the first conductive pads;

removing the first insulating layer to expose a sidewall of the first conductive pads;

providing a semiconductor die including a plurality of interconnect structures formed over a surface of the semiconductor die; and

disposing the semiconductor die over the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structures to the first conductive pads.

7. The method of claim 6 , further including:

forming a second insulating layer with patterned openings disposed over the first conductive pads; and

forming the recesses through a surface of the first conductive pads within the patterned openings of the second insulating layer.

8. The method of claim 6 , further including:

forming a second insulating layer with patterned openings disposed over the first conductive pads; and

forming a second conductive pad within the patterned openings of the second insulating layer.

9. The method of claim 6 , further including:

forming a first conductive layer over the substrate;

forming a second insulating layer over the first insulating layer with patterned openings in the second insulating layer disposed over the first conductive layer;

forming a second conductive layer over the first conductive layer within the patterned openings of the second insulating layer; and

forming the first conductive pads over the second conductive layer within the patterned openings of the second insulating layer.

10. The method of claim 6 , further including depositing a mold underfill material between the semiconductor die and substrate.

11. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first insulating layer over the substrate including a plurality of openings disposed over the substrate;

forming a plurality of first conductive pads within the openings of the first insulating layer over the substrate;

expanding an interconnect surface area of the first conductive pads by forming a plurality of recesses partially into the first conductive pads while retaining a portion of the first conductive pads under the recesses;

removing the first insulating layer to expose sidewalls of the first conductive pads; and

disposing a semiconductor die over the substrate including a plurality of bumps contacting the interconnect surface area and sidewalls of the first conductive pads.

12. The method of claim 11 , further including:

forming a second insulating layer with patterned openings disposed over the first conductive pads; and

forming the recesses through a surface of the first conductive pads within the patterned openings of the second insulating layer.

13. The method of claim 11 , further including:

forming a second insulating layer with patterned openings disposed over the first conductive pads; and

forming a second conductive pad within the patterned openings of the second insulating layer.

14. The method of claim 11 , further including:

forming a first conductive layer over the substrate;

forming a second insulating layer over the substrate with patterned openings in the second insulating layer disposed over the first conductive layer;

forming a second conductive layer over the first conductive layer within the patterned openings of the second insulating layer; and

forming the first conductive pads over the second conductive layer within the patterned openings of the second insulating layer.

15. A semiconductor device, comprising:

a substrate;

a plurality of first conductive pads formed over the substrate, the first conductive pads including an expanded interconnect surface area comprising a sidewall of the first conductive pads and a plurality of recesses formed partially into the first conductive pads while retaining a portion of the first conductive pads under the recesses; and

a semiconductor die including a plurality of interconnect structures formed over a surface of the semiconductor die, wherein the semiconductor die is disposed over the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structures to the first conductive pads.

16. The semiconductor device of claim 15 , further including:

a first conductive layer formed over the substrate;

a first insulating layer formed over the first conductive layer and substrate;

a second insulating layer formed over the first insulating layer with patterned openings in the second insulating layer disposed over the first conductive layer;

a second conductive layer formed over the first conductive layer within the patterned openings of the second insulating layer; and

the first conductive pads formed over the second conductive layer within the patterned openings of the second insulating layer.

17. The semiconductor device of claim 15 , further including a mold underfill material deposited between the semiconductor die and substrate.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON THE COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065239/0786 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0244 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2011
From: CHOI, DAESIK; KIM, OHHAN; CHO, SUNGWON
To: STATS CHIPPAC, LTD.
Reel/Frame 026365/0155 →