Patent Assignment
Reel/Frame 038378/0244
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 8
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET, SINGAPORE, SGX, SINGAPORE
Covered Applications
(79)
THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
App. No. 13/438,155
→
METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 13/431,816
→
METHOD OF FORMING TOP ELECTRODE FOR CAPACITOR AND INTERCONNECTION IN INTEGRATED PASSIVE DEVICE (IPD)
App. No. 13/355,354
→
COOPERATING DEFIBRILLATORS AND EXTERNAL CHEST COMPRESSION DEVICES
App. No. 13/352,055
→
METHOD FOR MANUFACTURE OF INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTECTED CONDUCTIVE LAYERS FOR PADS
App. No. 13/233,402
→
Semiconductor Device and Method of Forming Dam Material Around Periphery of Die to Reduce Warpage
App. No. 13/223,478
→
SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING BALUN AND RF COUPLER ON A COMMON SUBSTRATE
App. No. 13/219,374
→
NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE GROUND SITES
App. No. 13/215,131
→
SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/211,698
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AFTER ENCAPSULATION AND GROUNDED THROUGH INTERCONNECT STRUCTURE
App. No. 13/209,620
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISOLATED PADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/197,122
→
Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant
App. No. 13/174,033
→
METHOD FOR MANUFACTURING WAFER SCALE HEAT SLUG SYSTEM
App. No. 13/161,008
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/161,368
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ISOLATION BARRIER AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/160,799
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 13/118,955
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
App. No. 13/149,669
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING EWLB PACKAGE CONTAINING STACKED SEMICONDUCTOR DIE ELECTRICALLY CONNECTED THROUGH CONDUCTIVE VIAS FORMED IN ENCAPSULANT AROUND DIE
App. No. 13/116,328
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/071,760
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME ETCHING AND METHOD OF MANUFACTURE THEREOF
App. No. 13/070,899
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/071,449
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIPCHIP LEADFRAME AND METHOD OF MANUFACTURE THEREOF
App. No. 13/070,291
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/053,719
→
SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBLE SPACER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/006,697
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/974,265
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPLE ROW LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/968,266
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ELECTRICAL INTERCONNECT WITH STRESS RELIEF VOID
App. No. 12/963,934
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/964,644
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD INTERLOCKING MECHANISMS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/961,494
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER ON CONDUCTIVE TRACES FOR ELECTRICAL ISOLATION IN FINE PITCH BONDING
App. No. 12/961,202
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/950,631
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME ELECTRICALLY CONNECTED TO EMBEDDED SEMICONDUCTOR DIE
App. No. 12/947,442
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH IMAGE SENSOR SYSTEM
App. No. 12/912,730
→
DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/912,728
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE TSV WITH INSULATING ANNULAR RING
App. No. 12/887,811
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DAM MATERIAL WITH OPENINGS AROUND SEMICONDUCTOR DIE FOR MOLD UNDERFILL USING DISPENSER AND VACUUM ASSIST
App. No. 12/885,831
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADDLE MOLDING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/884,073
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/882,067
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
App. No. 12/882,110
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIFFERENT HEIGHT CONDUCTIVE PILLARS TO ELECTRICALLY INTERCONNECT STACKED LATERALLY OFFSET SEMICONDUCTOR DIE
App. No. 12/876,013
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME OVER SEMICONDUCTOR DIE TO PROVIDE VERTICAL INTERCONNECT
App. No. 12/875,981
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOUNTING
App. No. 12/875,998
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
App. No. 12/858,602
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING
App. No. 12/834,176
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STAND-OFF AND METHOD OF MANUFACTURE THEREOF
App. No. 12/822,659
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECT STRUCTURE ON LEADFRAME
App. No. 12/822,504
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS AND HEAT SINK OVER SEMICONDUCTOR DIE USING LEADFRAME
App. No. 12/787,973
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED MULTI-DIE LEADFRAME FOR ELECTRICAL INTERCONNECT OF STACKED SEMICONDUCTOR DIE
App. No. 12/781,751
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH REINFORCED ENCAPSULANT HAVING EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/777,415
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
App. No. 12/768,177
→
SEMICONDUCTOR METHOD OF FORMING BUMP ON SUBSTRATE TO PREVENT ELK ILD DELAMINATION DURING REFLOW PROCESS
App. No. 12/764,805
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING OPTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/731,870
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP CONTACT ON PACKAGE LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/726,342
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
App. No. 12/720,057
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AIR GAP ADJACENT TO STRESS SENSITIVE REGION OF THE DIE
App. No. 12/699,431
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/639,984
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/636,779
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CAVITY AND METHOD OF MANUFACTURE THEREOF
App. No. 12/582,582
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CIRCUITRY STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/562,722
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIRECTIONAL RF COUPLER WITH IPD FOR ADDITIONAL RF SIGNAL PROCESSING
App. No. 12/557,382
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/544,578
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY IN BUILD-UP INTERCONNECT STRUCTURE FOR SHORT SIGNAL PATH BETWEEN DIE
App. No. 12/537,824
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SPREADER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/412,315
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 12/411,154
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER BETWEEN STACKED SEMICONDUCTOR DIE
App. No. 12/411,310
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED CONFIGURATION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/410,983
→
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/331,341
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS EMBEDDED IN PHOTOSENSITIVE ENCAPSULANT
App. No. 12/329,430
→
WIRE-ON-LEAD PACKAGE SYSTEM HAVING LEADFINGERS POSITIONED BETWEEN PADDLE EXTENSIONS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/328,764
→
METHOD AND APPARATUS FOR A PACKAGE HAVING MULTIPLE STACKED DIE
App. No. 12/060,115
→
SEMICONDUCTOR MULTI-PACKAGE MODULE INCLUDING TAPE SUBSTRATE LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
App. No. 12/059,077
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREFOR
App. No. 12/057,360
→
SEMICONDUCTOR DEVICE AND METHOD OF MAKING INTEGRATED PASSIVE DEVICES
App. No. 11/949,255
→
CIRCUIT SYSTEM WITH CIRCUIT ELEMENT AND REFERENCE PLANE
App. No. 11/769,296
→
INTEGRATED CIRCUIT PACKAGE TO PACKAGE STACKING SYSTEM
App. No. 11/382,983
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEATSPREADER
App. No. 11/278,008
→
INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
App. No. 11/276,942
→
INTER-STACKING MODULE SYSTEM
App. No. 11/330,930
→
NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/164,335
→