IP Library Granted Patent US 8,378,383
Granted Patent B2
US 8,378,383 · App. 12/411,310 · Granted Feb 19, 2013

Semiconductor device and method of forming a shielding layer between stacked semiconductor die

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Quick Facts
Patent No.
US 8,378,383
App. No.
12/411,310
Granted
Feb 19, 2013
Kind
B2
Abstract

A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.

Claims (64)

1. A method of manufacturing a semiconductor device, comprising:

providing a first semiconductor die having an active surface;

forming a shielding layer over a back surface of the first semiconductor die opposite the active surface;

providing a sacrificial carrier;

leading with the active surface, mounting the first semiconductor die to the sacrificial carrier;

forming a first insulating layer over the shielding layer;

mounting a second semiconductor die over the first semiconductor die separated by the shielding layer and first insulating layer;

depositing a second insulating layer over the first and second semiconductor die;

forming a first interconnect structure over the second semiconductor die and second insulating layer;

removing the sacrificial carrier; and

forming a second interconnect structure over the first semiconductor die and second insulating layer.

2. The method of claim 1 , further including:

forming a conductive layer over the sacrificial carrier; and

forming a conductive pillar over the conductive layer, the conductive pillar being electrically connected between the first and second interconnect structures.

3. The method of claim 1 , further including electrically connecting the shielding layer to the second interconnect structure with a bond wire.

4. The method of claim 1 , further including electrically connecting the shielding layer to the second interconnect structure with a redistribution layer.

5. The method of claim 1 , further including:

forming a through silicon via in the first semiconductor die; and

electrically connecting the shielding layer to the second interconnect structure with the through silicon via.

6. The method of claim 1 , wherein forming the first and second interconnect structure includes:

forming a plurality of conductive layers; and

forming a plurality of insulating layers between the conductive layers.

7. The method of claim 1 , further including electrically connecting the shielding layer to a low-impedance ground point.

8. A method of manufacturing a semiconductor device, comprising:

providing a first semiconductor die having an active surface;

forming a first shielding layer over a back surface of the first semiconductor die opposite its active surface;

providing a second semiconductor die having an active surface;

forming a second shielding layer over a back surface of the second semiconductor die opposite its active surface;

mounting the second semiconductor to the first semiconductor by bonding the second shielding layer to the first shielding layer;

depositing a first insulating layer over the first and second semiconductor die;

forming a first interconnect structure over the second semiconductor die and first insulating layer; and

forming a second interconnect structure over the first semiconductor die and first insulating layer.

9. The method of claim 8 , further including forming a conductive pillar between the first and second interconnect structures.

10. The method of claim 8 , further including electrically connecting the first and second shielding layers to the second interconnect structure with a bond wire or redistribution layer.

11. The method of claim 8 , further including:

forming a through silicon via in the first semiconductor die; and

electrically connecting the first and second shielding layers to the second interconnect structure with the through silicon via.

12. The method of claim 8 , further including forming a second insulating layer over the first shielding layer.

13. The method of claim 8 , further including electrically connecting the first and second shielding layers to a low-impedance ground point.

14. A method of manufacturing a semiconductor device, comprising:

disposing a first shielding layer between first and second semiconductor die;

depositing a first insulating layer over the first and second semiconductor die; and

forming a first interconnect structure over the second semiconductor die and first insulating layer.

15. The method of claim 14 , further including forming a second interconnect structure over the first semiconductor die and first insulating layer.

16. The method of claim 15 , further including forming a conductive pillar between the first and second interconnect structures.

17. The method of claim 15 , further including electrically connecting the first shielding layer to the second interconnect structure with a bond wire or redistribution layer.

18. The method of claim 15 , further including:

forming a through silicon via in the first semiconductor die; and

electrically connecting the first shielding layer to the second interconnect structure with the through silicon via.

19. The method of claim 14 , further including disposing a second shielding layer between first and second semiconductor die.

20. The method of claim 14 , further including forming a second insulating layer over the first shielding layer.

21. A method of manufacturing a semiconductor device, comprising:

providing a first semiconductor die;

forming a shielding layer over a surface of the first semiconductor die;

mounting a second semiconductor die over the first semiconductor die separated by the shielding layer;

depositing an insulating layer around the first and second semiconductor die; and

forming a first interconnect structure over the second semiconductor die and insulating layer.

22. The method of claim 21 , further including forming a second interconnect structure over the first semiconductor die and insulating layer.

23. The method of claim 22 , further including forming a conductive pillar between the first and second interconnect structures.

24. The method of claim 22 , further including forming a bond wire between the shielding layer and second interconnect structure.

25. The method of claim 22 , further including:

forming a through silicon via in the first semiconductor die; and

electrically connecting the shielding layer to the second interconnect structure with the through silicon via.

26. The method of claim 21 , further including electrically connecting the shielding layer to a low-impedance ground point.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON THE COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065239/0786 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0244 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2009
From: PAGAILA, REZA A.; DO, BYUNG TAI; SUTHIWONGSUNTHORN, NATHAPONG
To: STATS CHIPPAC, LTD.
Reel/Frame 022451/0978 →