IP Library Granted Patent US 8,409,917
Granted Patent B2
US 8,409,917 · App. 13/053,719 · Granted Apr 2, 2013

Integrated circuit packaging system with an interposer substrate and method of manufacture thereof

Inventors: In Sang Yoon (Ichon-si, KR); HeeJo Chi (Ichon-si, KR); HanGil Shin (Seongnam-si, KR)
Assignee: STATS ChipPAC Ltd.
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Quick Facts
Patent No.
US 8,409,917
App. No.
13/053,719
Granted
Apr 2, 2013
Kind
B2
Abstract

A method of manufacturing of an integrated circuit packaging system includes: providing a base substrate; mounting a first die over the base substrate; mounting a second die over the first die; attaching an interposer substrate over the first die with an attachment adhesive therebetween, the interposer substrate having a central cavity and the second die within the central cavity; attaching a lateral interconnect to a second active side away from the first die of the second die and to the interposer substrate; and encapsulating the first die and the second die.

Claims (59)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a base substrate;

mounting a first die over the base substrate;

mounting a middle die on an active side of the first die;

mounting a second die on a middle active side of the middle die on the active side of the first die;

attaching base interconnects to the base substrate;

attaching an interposer substrate over the first die with an attachment adhesive therebetween, the interposer substrate having a central cavity with the second die within the central cavity and the base interconnects connected to the interposer substrate and the base substrate;

attaching a lateral interconnect to a second active side of the second die away from the first die and to the interposer substrate; and

encapsulating the base interconnects, the first die, and the second die in a single molding process.

2. The method as claimed in claim 1 wherein encapsulating the first die and the second die includes forming a cap protrusion over the central cavity and covering the lateral interconnect.

3. The method as claimed in claim 1 further comprising

encapsulating the middle die.

4. The method as claimed in claim 1 further comprising:

mounting a top die over the second die and the interposer substrate, the top die having a top interconnects attached the interposer substrate; and

wherein:

encapsulating the first die and the second die includes encapsulating the top die.

5. The method as claimed in claim 1 wherein attaching the interposer substrate over the first die with the attachment adhesive therebetween includes applying an epoxy dot as the attachment adhesive.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a base substrate;

mounting a first die over the base substrate;

mounting a middle die on an active side of the first die;

mounting a second die on a middle active side of the middle die on the active side of the first die;

attaching base interconnects, to the base substrate, in multiple rows around the first die;

attaching an interposer substrate over the first die with an attachment adhesive therebetween having a central cavity supported by the base interconnects, the base interconnects on the base substrate and the second die within the central cavity;

attaching a lateral interconnect to a second active side of the second die away from the first die and to the interposer substrate; and

encapsulating the base interconnects, the first die, and the second die in a single molding process.

7. The method as claimed in claim 6 wherein encapsulating the first die and the second die includes encapsulating the first die and the second die having at least one surface of the interposer substrate exposed.

8. The method as claimed in claim 6 wherein attaching the interposer substrate over the first die with the attachment adhesive therebetween includes applying the attachment adhesive around a peripheral region of the first die, the peripheral region facing away from the base substrate.

9. The method as claimed in claim 6 further comprising:

mounting a top external interconnects over the interposer substrate; and

wherein:

encapsulating the first die and the second die includes encapsulating the first die and the second die having the top external interconnects and the base substrate exposed.

10. The method as claimed in claim 6 wherein attaching the interposer substrate over the first die with the attachment adhesive therebetween having the central cavity supported by the base interconnects for electrical connection and structural spacing.

11. An integrated circuit packaging system comprising:

a base substrate;

a first die mounted over the base substrate;

an attachment adhesive over the first die;

a middle die on an active side of the first die;

base interconnects attached on the base substrate around the first die;

an interposer substrate over the attachment adhesive and coupled to the base interconnects, the interposer substrate having a central cavity;

a second die mounted on a middle active side of the middle die on the active side of the first die and in the central cavity;

a lateral interconnect attached to a second active side of the second die away from the first die and to the interposer substrate; and

a single encapsulation formed on the base interconnects, the first die, and the second die.

12. The system as claimed in claim 11 wherein the encapsulation includes a cap protrusion around the lateral interconnect.

13. The system as claimed in claim 11 wherein

the encapsulation surrounds the middle die.

14. The system as claimed in claim 11 further comprising:

a top die mounted over the second die and the interposer substrate, the top die having a top interconnects attached to the interposer substrate; and

wherein:

the encapsulation encapsulates the top die.

15. The system as claimed in claim 11 wherein the attachment adhesive is an epoxy dot.

16. The system as claimed in claim 11 wherein the base interconnects attached on the base substrate includes a double row of the base interconnects around the first die.

17. The system as claimed in claim 16 wherein the encapsulation leaves at least one surface of the interposer substrate exposed.

18. The system as claimed in claim 16 wherein the attachment adhesive is around a peripheral region of the first die, the peripheral region facing away from the base substrate.

19. The system as claimed in claim 16 further comprising:

a top external interconnects mounted on the interposer substrate; and

wherein:

the encapsulation exposes the top external interconnects and the base substrate.

20. The system as claimed in claim 16 wherein the base interconnects are for electrical connection and structural spacing between the interposer substrate and the first die.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON THE COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065239/0786 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0244 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2011
From: YOON, IN SANG; CHI, HEEJO; SHIN, HANGIL
To: STATS CHIPPAC LTD.
Reel/Frame 026063/0848 →
Continuity (1)
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