Thermally enhanced semiconductor package system

1. A semiconductor package system comprising:

a semiconductor chip;

a substrate having a substrate opening and a vertical build-up wing, the substrate having the semiconductor chip mounted thereon with the vertical build-up wing circumscribed by vertical planes of a perimeter of, and spaced apart from, the semiconductor chip;

a first heat slug attached above the substrate at a first horizontal plane and to a first surface of the semiconductor chip, the semiconductor chip at least partially encapsulated by the first heat slug; and

a second heat slug attached to the substrate at a second horizontal plane above the first horizontal plane and to a second surface of the semiconductor chip through the substrate opening.

2. The system as claimed in claim 1 further comprising:

solder pillars/bail bumps formed on the substrate; and

stud bumps for conductively connecting the semiconductor chip to the solder pillars/ball bumps on the substrate.

3. The system as claimed in claim 1 further comprising:

a solder mask on the substrate within the vertical built-up wing.

4. The system as claimed in claim 1 wherein:

the first heat slug further comprises a top recess on a top surface thereof;

the second heat slug further comprises a bottom recess on a bottom surface thereof; or

the first and second heat slugs provide at least 80% of the surface area of the semiconductor package system.

5. The system as claimed in claim wherein:

the first heat slug further comprises a first fin on a top surface thereof; or

the second heat slug further comprises a second fin on a bottom surface thereof.