Integrated circuit packaging system with transparent encapsulation and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: forming a substrate having a redistribution line thereon; mounting an integrated circuit to the substrate; and molding a transparent encapsulation over the substrate covering the integrated circuit and the redistribution line and the integrated circuit seen through the transparent encapsulation.
1. A method of manufacture of an integrated circuit packaging system comprising:
forming a substrate having a redistribution line thereon;
mounting an integrated circuit to the substrate;
forming a mounting interconnect on the substrate;
molding a transparent encapsulation over the substrate covering the integrated circuit and the redistribution line and the integrated circuit seen through the transparent encapsulation; and
forming a hole in the transparent encapsulation to the mounting interconnect.
2. The method as claimed in claim 1 further comprising forming a conductive channel through the transparent encapsulation to the substrate.
3. The method as claimed in claim 1 wherein forming the substrate includes forming a through-silicon-via substrate.
4. The method as claimed in claim 1 further comprising forming a conductive line on the transparent encapsulation.
5. A method of manufacture of an integrated circuit packaging system comprising:
forming a substrate having a redistribution line thereon;
mounting an integrated circuit to the substrate;
forming a mounting interconnect on the substrate;
molding a transparent encapsulation over the substrate covering the integrated circuit and the redistribution line and the integrated circuit seen through the transparent encapsulation with the transparent encapsulation having a transmittance of over 95% of light with a wavelength between 450 nm and 1300 nm; and
forming a hole in the transparent encapsulation to the mounting interconnect.
6. The method as claimed in claim 5 further comprising:
forming a mounting interconnect on the substrate;
aligning a location for a hole over the mounting interconnect through the transparent encapsulation; and
forming the hole in the transparent encapsulation at the location.
7. The method as claimed in claim 5 further comprising:
forming a conductive channel through the transparent encapsulation to the substrate; and
forming a conductive line on the transparent encapsulation and to the conductive channel.
8. The method as claimed in claim 5 wherein:
forming the substrate includes forming a contact on the substrate; and further comprising:
aligning a location for a conductive channel to the contact through the transparent encapsulation; and
forming the conductive channel through the transparent encapsulation at the location.
9. The method as claimed in claim 5 wherein molding the transparent encapsulation includes forming the transparent encapsulation having a coefficient of thermal expansion approximately between 43 ppm/° C. and 142 ppm/° C.
10. An integrated circuit packaging system comprising:
a substrate having a redistribution line thereon;
an integrated circuit mounted to the substrate;
a mounting interconnect on the substrate;
a transparent encapsulation over the substrate covering the integrated circuit and the redistribution line and the integrated circuit seen through the transparent encapsulation; and
a hole in the transparent encapsulation to the mounting interconnect.
11. The system as claimed in claim 10 further comprising a conductive channel through the transparent encapsulation to the substrate.
12. The system as claimed in claim 10 wherein the substrate includes a through-silicon-via substrate.
13. The system as claimed in claim 10 further comprising forming a conductive line on the transparent encapsulation.
14. The system as claimed in claim 10 wherein the transparent encapsulation has a transmittance of over 95% of light with a wavelength between 450 nm and 1300 nm.
15. The system as claimed in claim 14 further comprising:
a mounting interconnect on the substrate; and wherein:
the transparent encapsulation includes a hole aligned to the mounting interconnect and exposes the mounting interconnect.
16. The system as claimed in claim 14 further comprising:
a conductive channel through the transparent encapsulation to the substrate; and
a conductive line on the transparent encapsulation and to the conductive channel.
17. The system as claimed in claim 14 wherein:
the substrate includes a contact; and further comprising:
a conductive channel through the transparent encapsulation to the contact.
18. The system as claimed in claim 14 wherein the transparent encapsulation has a coefficient of thermal expansion approximately between 43 ppm/° C. and 142 ppm/° C.