IP Library Granted Patent US 8,372,695
Granted Patent B2
US 8,372,695 · App. 12/950,631 · Granted Feb 12, 2013

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,372,695
App. No.
12/950,631
Granted
Feb 12, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a substrate base side and a substrate stack side; mounting an integrated circuit over the substrate stack side; attaching a stack connector to the substrate stack side; forming an encapsulation over the stack connector and the integrated circuit; attaching an external connector to the substrate base side; attaching an adhesive tape to the external connector having spacing between the adhesive tape and the substrate base side; cutting a step portion in the encapsulation to expose the stack connector; cutting a singulation kerf in the package substrate having exit damage on the substrate base side; and removing the adhesive tape.

Claims (31)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a package substrate having a substrate base side and a substrate stack side;

mounting an integrated circuit over the substrate stack side;

attaching a stack connector to the substrate stack side;

forming an encapsulation over the stack connector and the integrated circuit;

attaching external connectors to the substrate base side;

attaching an adhesive tape to the external connectors having spacing between the adhesive tape and the substrate base side;

cutting a step portion in the encapsulation to expose the stack connector after attaching the adhesive tape to the external connectors;

cutting a singulation kerf in the package substrate; and

removing the adhesive tape.

2. The method as claimed in claim 1 wherein cutting the step portion includes cutting the step portion in the encapsulation having a protrusion surrounded by the step portion.

3. The method as claimed in claim 1 wherein cutting the step portion includes cutting the step portion in the encapsulation to expose the stack connector having a stack end coplanar with a step top side of the step portion.

4. The method as claimed in claim 1 wherein cutting the step portion includes cutting the step portion in the encapsulation having a protrusion extending from a step top side of the step portion.

5. The method as claimed in claim 1 wherein attaching the stack connector includes attaching stack connectors to the substrate stack side.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a package substrate having a substrate base side and a substrate stack side;

mounting an integrated circuit over the substrate stack side;

connecting a device connector to the integrated circuit and the substrate stack side;

attaching a stack connector to the substrate stack side;

forming an encapsulation over the stack connector and the integrated circuit;

attaching external connectors to the substrate base side;

attaching an adhesive tape to the external connectors having spacing between the adhesive tape and the substrate base side;

cutting a step portion in the encapsulation to expose the stack connector after attaching the adhesive tape to the external connectors;

cutting a singulation kerf in the package substrate; and

removing the adhesive tape.

7. The method as claimed in claim 6 wherein cutting the step portion includes cutting the step portion in the encapsulation having a protrusion surrounded by the step portion and over the device connector.

8. The method as claimed in claim 6 wherein cutting the step portion includes cutting the step portion in the encapsulation to expose the stack connector having a stack end coplanar with a step top side of the step portion, the stack connector adjacent the device connector.

9. The method as claimed in claim 6 wherein cutting the step portion includes cutting the step portion in the encapsulation having a protrusion covering the integrated circuit and extending from a step top side of the step portion.

10. The method as claimed in claim 6 wherein:

attaching the stack connector includes attaching stack connectors to the substrate stack side; and

cutting the step portion includes cutting the step portion in the encapsulation having a protrusion surrounded by the stack connectors.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON THE COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065239/0786 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0244 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2010
From: PARK, SANGMI; KIM, MINJUNG
To: STATS CHIPPAC LTD.
Reel/Frame 025487/0814 →