Patent Assignment
Reel/Frame 038378/0391
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 9
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(82)
Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
App. No. 14/181,429
→
Flip Chip Interconnection Structure
App. No. 14/170,295
→
Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
App. No. 14/160,796
→
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
App. No. 14/154,049
→
SEMICONDUCTOR DEVICE AND METHOD OF CONFINING CONDUCTIVE BUMP MATERIAL WITH SOLDER MASK PATCH
App. No. 14/144,906
→
Semiconductor Device and Method of Making TSV Interconnect Structures Using Encapsulant for Structural Support
App. No. 14/143,891
→
Semiconductor Package and Method of Mounting Semiconductor Die to Opposite Sides of TSV Substrate
App. No. 14/138,646
→
Semiconductor Device and Method of Forming Non-Linear Interconnect Layer with Extended Length for Joint Reliability
App. No. 14/138,382
→
Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units
App. No. 14/135,415
→
SEMICONDUCTOR DEVICE AND METHOD OF USING A STANDARDIZED CARRIER IN SEMICONDUCTOR PACKAGING
App. No. 14/097,534
→
SEMICONDUCTOR DEVICE INCLUDING INTEGRATED PASSIVE DEVICE FORMED OVER SEMICONDUCTOR DIE WITH CONDUCTIVE BRIDGE AND FAN-OUT REDISTRIBUTION LAYER
App. No. 14/092,304
→
SEMICONDUCTOR DEVICE WITH DUMMY METAL PROTECTIVE STRUCTURE AROUND SEMICONDUCTOR DIE FOR LOCALIZED PLANARIZATION OF INSULATING LAYER
App. No. 14/090,036
→
Semiconductor Device with Protective Layer Over Exposed Surfaces of Semiconductor Die
App. No. 14/087,653
→
Semiconductor Device and Method of Forming Multi-Layered UBM with Intermediate Insulating Buffer Layer to Reduce Stress for Semiconductor Wafer
App. No. 14/084,745
→
Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding
App. No. 14/082,155
→
Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants
App. No. 14/080,609
→
Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP
App. No. 14/079,273
→
SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURE
App. No. 14/063,274
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A FAN-OUT POP DEVICE WITH PWB VERTICAL INTERCONNECT UNITS
App. No. 14/061,244
→
Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP
App. No. 14/043,751
→
Semiconductor Device and Method of Forming Low Profile Fan-Out Package with Vertical Interconnection Units
App. No. 14/038,575
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MOLD UNDERFILL USING DISPENSING NEEDLE HAVING SAME WIDTH AS SEMICONDUCTOR DIE
App. No. 14/020,996
→
Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect Structure
App. No. 14/021,056
→
Optical Semiconductor Device Having Pre-Molded Leadframe with Window and Method Therefor
App. No. 14/021,208
→
Semiconductor Device and Method of Forming Electrical Interconnection Between Semiconductor Die and Substrate with Continuous Body of Solder Tape
App. No. 14/021,740
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY ADJACENT TO SENSITIVE REGION OF SEMICONDUCTOR DIE USING WAFER-LEVEL UNDERFILL MATERIAL
App. No. 14/021,206
→
Semiconductor Device and Method of Forming Bump-on-Lead Interconnection
App. No. 14/021,914
→
SEMICONDUCTOR DEVICE HAVING BALANCED BAND-PASS FILTER IMPLEMENTED WITH LC RESONATORS
App. No. 14/018,282
→
Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation
App. No. 14/017,963
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A WAFER LEVEL PACKAGE WITH TOP AND BOTTOM SOLDER BUMP INTERCONNECTION
App. No. 14/011,491
→
Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die
App. No. 13/944,825
→
Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material
App. No. 13/944,783
→
Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
App. No. 13/943,735
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPEN CAVITY IN TSV INTERPOSER TO CONTAIN SEMICONDUCTOR DIE IN WLCSMP
App. No. 13/943,737
→
Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer
App. No. 13/939,044
→
Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure
App. No. 13/937,952
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PENETRABLE FILM ENCAPSULANT AROUND SEMICONDUCTOR DIE AND INTERCONNECT STRUCTURE
App. No. 13/937,849
→
Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
App. No. 13/935,963
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING TSV SEMICONDUCTOR WAFER WITH EMBEDDED SEMICONDUCTOR DIE
App. No. 13/936,099
→
SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE
App. No. 13/935,053
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER OVER A SEMICONDUCTOR DIE DISPOSED IN A CAVITY OF AN INTERCONNECT STRUCTURE AND GROUNDED THROUGH THE DIE TSV
App. No. 13/935,312
→
Semiconductor Device and Method of Forming a Thin Wafer Without a Carrier
App. No. 13/933,406
→
Semiconductor Method and Device of Forming a Fan-Out Device with PWB Vertical Interconnect Units
App. No. 13/917,982
→
SYSTEM-IN-PACKAGE HAVING INTEGRATED PASSIVE DEVICES AND METHOD THEREFOR
App. No. 13/910,786
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED HEAT SPREADER FRAME WITH EMBEDDED SEMICONDUCTOR DIE
App. No. 13/906,667
→
SEMICONDUCTOR DEVICE WITH BUMP FORMED ON SUBSTRATE TO PREVENT ELK ILD DELAMINATION DURING REFLOW PROCESS
App. No. 13/906,844
→
Semiconductor Device and Method of Forming Protective Coating Material Over Semiconductor Wafer to Reduce Lamination Tape Residue
App. No. 13/906,489
→
SEMICONDUCTOR DEVICE AND METHOD OF CONFINING CONDUCTIVE BUMP MATERIAL DURING REFLOW WITH SOLDER MASK PATCH
App. No. 13/905,845
→
Semiconductor Device and Method of Forming Reconstituted Wafer With Larger Carrier to Achieve More EWLB Packages Per Wafer with Encapsulant Deposited Under Temperature and Pressure
App. No. 13/906,060
→
Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die
App. No. 13/896,635
→
METHOD OF FORMING RDL WIDER THAN CONTACT PAD ALONG FIRST AXIS AND NARROWER THAN CONTACT PAD ALONG SECOND
App. No. 13/893,616
→
Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die
App. No. 13/886,556
→
Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP
App. No. 13/887,180
→
Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers
App. No. 13/874,150
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING COVER TO SEMICONDUCTOR DIE AND INTERPOSER WITH ADHESIVE MATERIAL
App. No. 13/871,157
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DUAL-SIDED INTERCONNECT STRUCTURES IN FO-WLCSP
App. No. 13/832,449
→
Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over Carrier for Testing at Interim Stages
App. No. 13/832,118
→
Semiconductor Device and Method of Forming Dual-Sided Interconnect Structures in FO-WLCSP
App. No. 13/832,205
→
Semiconductor Device having Wire Studs as Vertical Interconnect in FO-WLP
App. No. 13/832,781
→
Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP
App. No. 13/832,809
→
SEMICONDUCTOR DEVICE AND METHOD OF USING SUBSTRATE HAVING BASE AND CONDUCTIVE POSTS TO FORM VERTICAL INTERCONNECT STRUCTURE IN EMBEDDED DIE PACKAGE
App. No. 13/800,807
→
Semiconductor Device and Method of Forming RDL Using UV-Cured Conductive Ink Over Wafer Level Package
App. No. 13/795,679
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF
App. No. 13/791,375
→
Semiconductor Device and Method of Forming Conductive Ink Layer as Interconnect Structure Between Semiconductor Packages
App. No. 13/653,242
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SUPPORTING LAYER OVER SEMICONDUCTOR DIE IN THIN FAN-OUT WAFER LEVEL CHIP SCALE PACKAGE
App. No. 13/630,912
→
Semiconductor Device and Method of Forming an Embedded SOP Fan-Out Package
App. No. 13/529,918
→
Semiconductor Device and Method of Reflow Soldering for Conductive Column Structure in Flip Chip Package
App. No. 13/489,143
→
SEMICONDUCTOR DEVICE AND METHOD OF BACKGRINDING AND SINGULATION OF SEMICONDUCTOR WAFER WHILE REDUCING KERF SHIFTING AND PROTECTING WAFER SURFACES
App. No. 13/488,029
→
Semiconductor Method and Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
App. No. 13/477,982
→
Semiconductor Device and Method of Controlling Warpage in Semiconductor Package
App. No. 13/471,314
→
Semiconductor Device and Method of Depositing Underfill Material With Uniform Flow Rate
App. No. 13/466,945
→
Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer
App. No. 13/428,439
→
SEMICONDUCTOR METHOD AND DEVICE OF FORMING A FAN-OUT POP DEVICE WITH PWB VERTICAL INTERCONNECT UNITS
App. No. 13/429,119
→
Semiconductor Device and Method of Simultaneous Testing of Multiple Interconnects for Electro-Migration
App. No. 13/426,576
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO-VIAS PARTIALLY THROUGH INSULATING MATERIAL OVER BUMP INTERCONNECT CONDUCTIVE LAYER FOR STRESS RELIEF
App. No. 13/426,552
→
SEMICONDUCTOR DEVICE AND METHOD OF SINGULATING SEMICONDUCTOR WAFER ALONG MODIFIED REGION WITHIN NON-ACTIVE REGION FORMED BY IRRADIATING ENERGY THROUGH MOUNTING TAPE
App. No. 13/426,416
→
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING OPENINGS AND TRENCHES IN INSULATING LAYER BY FIRST LDA AND SECOND LDA FOR RDL FORMATION
App. No. 13/426,561
→
Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
App. No. 13/424,710
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE LAYER OVER METAL SUBSTRATE FOR ELECTRICAL INTERCONNECT OF SEMICONDUCTOR DIE
App. No. 13/425,349
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPLIANT CONDUCTIVE INTERCONNECT STRUCTURE IN FLIPCHIP PACKAGE
App. No. 13/422,981
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING
App. No. 11/766,787
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COMMUNICATION BETWEEN EMERGENCY MEDICAL DEVICE AND SAFETY AGENCY
App. No. 10/335,542
→