Semiconductor Device and Method of Forming Reconstituted Wafer With Larger Carrier to Achieve More EWLB Packages Per Wafer with Encapsulant Deposited Under Temperature and Pressure
A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer.
1 . A semiconductor device, comprising:
a semiconductor wafer;
a plurality of semiconductor die singulated from the semiconductor wafer;
a carrier including a surface area larger than a surface area of the semiconductor wafer, wherein the semiconductor die are disposed side-by-side over the carrier to form a reconstituted wafer and a number of semiconductor die disposed over the carrier is greater than a total number of semiconductor die singulated from the semiconductor wafer; and
an encapsulant deposited over the semiconductor die.
2 . The semiconductor device of claim 1 , wherein the encapsulant is planarized to expose a surface of the semiconductor die.
3 . The semiconductor device of claim 1 , further including:
an upper mold support including the cavity; and
a lower mold support with spring-loaded lifter pins, wherein the reconstituted wafer is disposed over the spring-loaded lifter pins between the upper mold support and lower mold support.
4 . The semiconductor device of claim 1 , wherein the surface area of the carrier is 10-50% greater than the surface area of the semiconductor wafer.
5 . The semiconductor device of claim 1 , further including an interconnect structure formed over the semiconductor die.
6 . The semiconductor device of claim 5 , wherein the interconnect structure includes:
a first insulating layer formed over the semiconductor die;
a conductive layer formed over the first insulating layer; and
a second insulating layer formed over the first insulating layer and conductive layer.
7 . A semiconductor device, comprising:
a plurality of semiconductor die originating from a semiconductor wafer; and
a carrier including a surface area larger than a surface area of the semiconductor wafer, wherein the semiconductor die are disposed side-by-side over a surface of the carrier to form a reconstituted wafer and a number of semiconductor die disposed over the carrier is greater than a total number of semiconductor die originating from the semiconductor wafer.
8 . The semiconductor device of claim 7 , further including an encapsulant deposited over the semiconductor die.
9 . The semiconductor device of claim 8 , wherein the encapsulant is planarized to expose a surface of the semiconductor die.
10 . The semiconductor device of claim 7 , further including:
an upper mold support including the cavity; and
a lower mold support with spring-loaded lifter pins, wherein the reconstituted wafer is disposed over the spring-loaded lifter pins between the upper mold support and lower mold support.
11 . The semiconductor device of claim 7 , wherein the surface area of the carrier is 10 - 50 % greater than the surface area of the semiconductor wafer.
12 . The semiconductor device of claim 7 , further including an interconnect structure formed over the semiconductor die.
13 . The semiconductor device of claim 12 , wherein the interconnect structure includes:
a first insulating layer formed over the semiconductor die;
a conductive layer formed over the first insulating layer; and
a second insulating layer formed over the first insulating layer and conductive layer.
14 . A semiconductor device, comprising:
a plurality of semiconductor die originating from a semiconductor wafer;
a carrier including a surface area larger than a surface area of the semiconductor wafer, wherein a number of the semiconductor die disposed over a surface of the carrier is greater than a total number of semiconductor die originating from the semiconductor wafer; and
an interconnect structure formed over the semiconductor die.
15 . The semiconductor device of claim 14 , further including an encapsulant deposited over the semiconductor die.
16 . The semiconductor device of claim 15 , wherein the encapsulant is planarized to expose a surface of the semiconductor die.
17 . The semiconductor device of claim 14 , further including:
an upper mold support including the cavity; and
a lower mold support with spring-loaded lifter pins, wherein the carrier is disposed over the spring-loaded lifter pins between the upper mold support and lower mold support.
18 . The semiconductor device of claim 14 , wherein the surface area of the carrier is 10 - 50 % greater than the surface area of the semiconductor wafer.
19 . The semiconductor device of claim 14 , wherein the interconnect structure includes:
a first insulating layer formed over the semiconductor die;
a conductive layer formed over the first insulating layer; and
a second insulating layer formed over the first insulating layer and conductive layer.
20 . A semiconductor device, comprising:
a plurality of semiconductor die originating from a semiconductor wafer; and
a carrier including a surface area larger than a surface area of the semiconductor wafer, wherein a number of the semiconductor die disposed over a surface of the carrier is greater than a total number of semiconductor die originating from the semiconductor wafer.
21 . The semiconductor device of claim 20 , further including an encapsulant deposited over the semiconductor die.
22 . The semiconductor device of claim 21 , wherein the encapsulant is planarized to expose a surface of the semiconductor die.
23 . The semiconductor device of claim 20 , wherein the surface area of the carrier is 10 - 50 % greater than the surface area of the semiconductor wafer.
24 . The semiconductor device of claim 20 , further including an interconnect structure formed over the semiconductor die.
25 . The semiconductor device of claim 24 , wherein the interconnect structure includes:
a first insulating layer formed over the semiconductor die;
a conductive layer formed over the first insulating layer; and
a second insulating layer formed over the first insulating layer and conductive layer.