Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.
1. A method of making a semiconductor device, comprising:
providing a substrate including a conductive via formed through the substrate;
disposing a modular interconnect unit including a vertical interconnect structure over the substrate;
disposing a first semiconductor die over the substrate;
depositing an encapsulant over the first semiconductor die and vertical interconnect structure;
planarizing the encapsulant to form a surface of the encapsulant coplanar with a back surface opposite an active surface of the first semiconductor die while leaving a portion of the encapsulant over the modular interconnect unit;
removing a portion of the encapsulant over the vertical interconnect structure to form an opening in the encapsulant after planarizing the encapsulant; and
disposing a second semiconductor die over the first semiconductor die including disposing a bump of the second semiconductor die within the opening of the encapsulant and electrically connected to the vertical interconnect structure.
2. The method of claim 1 , further including forming a conductive layer over the substrate.
3. The method of claim 1 , further including removing a portion of the substrate over the conductive via.
4. The method of claim 1 , wherein a height of the vertical interconnect structure is less than a height of the first semiconductor die.
5. The method of claim 1 , further including disposing a third semiconductor die over the substrate, wherein the modular interconnect unit is disposed between the first semiconductor die and the third semiconductor die.
6. The method of claim 1 , wherein the vertical interconnect structure is a conductive via.