IP Library Patent Application 13477982
Patent Application
App. No. 13/477,982

Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units

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Quick Facts
Patent No.
US None
App. No.
13/477,982
Abstract

A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Claims (47)

1 . A method of making a semiconductor device, comprising:

providing a carrier with a die attach area;

mounting a first semiconductor die to the die attach area;

mounting a modular interconnect unit over the carrier in a peripheral region around the first semiconductor die;

depositing a first encapsulant over the carrier, first semiconductor die, and modular interconnect unit;

removing a portion of the first encapsulant to expose the first semiconductor die and modular interconnect unit;

removing the carrier; and

forming an interconnect structure over the first semiconductor die and modular interconnect unit.

2 . The method of claim 1 , wherein the modular interconnect unit includes a core with a vertical interconnect structure formed through the core and overlapping the core by 0-200 micrometers.

3 . The method of claim 2 , wherein the vertical interconnect structure includes an opening filled with a conductive paste or polymer plug.

4 . The method of claim 1 , wherein the modular interconnect unit is offset from the semiconductor die and a height of the modular interconnect unit is less than a height of the semiconductor die.

5 . The method of claim 1 , further including:

providing a second semiconductor die; and

mounting the second semiconductor die to the modular interconnect unit.

6 . The method of claim 1 , wherein the modular interconnect unit is formed from a second encapsulant or a printed circuit board (PCB) with a coefficient of thermal expansion (CTE) greater than the CTE of the first encapsulant.

7 . A method of making a semiconductor device, comprising:

providing a carrier;

mounting a modular interconnect unit over the carrier in a peripheral region of the semiconductor die;

mounting a semiconductor die to the carrier;

depositing an encapsulant over the carrier, semiconductor die, and modular interconnect unit; and

removing a portion of the encapsulant to expose the modular interconnect unit and the semiconductor die.

8 . The method of claim 7 , wherein the modular interconnect unit includes a core with a vertical interconnect structure formed through the core.

9 . The method of claim 7 , wherein the modular interconnect unit has a square shape, rectangular shape, cross-shape, angled or L-shape, circular shape, or oval shape.

10 . The method of claim 7 , further including forming an insulating layer over a back surface of the semiconductor die prior to exposing the modular interconnect unit with respect to the encapsulant.

11 . The method of claim 7 , wherein removing the portion of encapsulant further includes:

removing a first portion of the encapsulant from over the semiconductor die to expose a back surface of the semiconductor die while leaving a second portion of the encapsulant over the modular interconnect unit; and

removing the second portion of the encapsulant to expose the modular interconnect unit.

12 . The method of claim 7 , wherein the modular interconnect unit forms part of an interlocking pattern around the semiconductor die and a height of the modular interconnect unit is less than a height of the semiconductor die.

13 . The method of claim 7 , further including forming an insulating layer over the semiconductor device to reduce warpage.

14 . A method of making a semiconductor device, comprising:

providing a semiconductor die;

disposing a modular interconnect unit in a peripheral region around the semiconductor die; and

depositing an encapsulant over the semiconductor die and modular interconnect unit.

15 . The method of claim 14 , wherein the modular interconnect unit includes a core with a conductive interconnect structure formed through the core.

16 . The method of claim 15 , wherein the conductive interconnect structure includes a metal cap and a protection layer formed over the metal cap.

17 . The method of claim 15 , wherein the modular interconnect unit includes multiple rows of vertical interconnect structures or bumps.

18 . The method of claim 14 , wherein the modular interconnect unit has a square shape, rectangular shape, cross-shape, angled or L-shape, circular shape, or oval shape.

19 . The method of claim 14 , further including forming a vertical interconnect structure through the modular interconnect unit after depositing the encapsulant over the semiconductor die and modular interconnect unit.

20 . The method of claim 14 , further including forming an insulating layer over the semiconductor device to reduce warpage.

21 . A semiconductor device, comprising:

a semiconductor die;

a modular interconnect unit disposed in a peripheral region around the semiconductor die; and

an encapsulant deposited around the semiconductor die and modular interconnect unit.

22 . The semiconductor device of claim 21 , wherein the modular interconnect unit includes a core with a vertical interconnect structure formed through the core.

23 . The semiconductor device of claim 21 , wherein the modular interconnect unit has a square shape, rectangular shape, cross-shape, angled or L-shape, circular shape, or oval shape.

24 . The semiconductor device of claim 21 , wherein the modular interconnect unit forms part of an interlocking pattern around the semiconductor die and a height of the modular interconnect unit is less than a height of the semiconductor die.

25 . The semiconductor device of claim 21 , further including an insulating layer formed over the semiconductor device to reduce warpage.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE. " TO STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0391. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064809/0877 →
RELEASE OF SECURITY INTEREST Recorded Jun 16, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052963/0546 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0391 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2012
From: LIN, YAOJIAN; MARIMUTHU, PANDI CHELVAM; CHEN, KANG; GU, YU
To: STATS CHIPPAC, LTD.
Reel/Frame 028251/0473 →