Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
disposing a modular interconnect unit including a plurality of interconnect structures adjacent to the semiconductor die;
depositing an encapsulant over the semiconductor die and modular interconnect unit;
removing a first portion of the encapsulant extending to a surface of the semiconductor die while leaving a second portion of the encapsulant over the modular interconnect unit;
forming a first insulating layer over the semiconductor die and modular interconnect unit;
forming a plurality of openings in the first insulating layer over a first interconnect structure of the plurality of interconnect structures with each opening of the plurality of openings extending to a surface of the first interconnect structure leaving a continuous portion of the first insulating layer between the plurality of openings over the surface of the first interconnect structure; and
forming a conductive layer over the first insulating layer and into the plurality of openings to contact the first interconnect structure.
2. The method of claim 1 , wherein the openings include a ring shape, cross shape, or lattice shape.
3. The method of claim 1 , further including forming a second insulating layer over the conductive layer, wherein the second insulating layer includes a thickness of less than 25 micrometers.
4. The method of claim 1 , further including planarizing a surface of the conductive layer.
5. The method of claim 1 , wherein a first opening of the plurality of openings includes a width of 20 to 30 micrometers.
6. A method of making a semiconductor device, comprising:
providing a semiconductor die;
disposing an interconnect unit including a conductive via in a peripheral region of the semiconductor die;
forming a first insulating layer over the semiconductor die and conductive via;
forming a first opening in the first insulating layer over the conductive via;
forming a second opening in the first insulating layer over the conductive via, wherein the first opening and second opening each include a width less than a width of the conductive via leaving a continuous portion of the first insulating layer around the first opening and second opening over the conductive via; and
forming a conductive layer over the first insulating layer and in the first opening and second opening of the first insulating layer over the conductive via.
7. The method of claim 6 , further including forming a second insulating layer over the conductive layer, wherein the second insulating layer includes a thickness of less than 25 micrometers.
8. The method of claim 6 , wherein the first opening includes a circular shape, ring shape, cross shape, or lattice shape.
9. The method of claim 6 , wherein the width of the first opening is 20 to 30 micrometers.
10. The method of claim 6 , wherein a pitch of the first opening and second opening is 40 micrometers.
11. The method of claim 6 , further including:
forming an encapsulant over the semiconductor die and conductive via; and
removing a portion of the encapsulant over the conductive via.
12. The method of claim 6 , further including:
forming an encapsulant over the semiconductor die and interconnect unit; and
removing a first portion of the encapsulant extending to a surface of the semiconductor die while leaving a second portion of the encapsulant over the interconnect unit.
13. A semiconductor device, comprising:
a semiconductor die;
an interconnect unit disposed in a peripheral region of the semiconductor die including an array of interconnect structures;
a first insulating layer formed over the interconnect unit, wherein the first insulating layer includes a plurality of individual openings formed over a first interconnect structure in the array of interconnect structures and extending to a surface of the first interconnect structure while leaving a portion of the first insulating layer between the plurality of individual openings over the surface of the first interconnect structure; and
a conductive layer formed over the first insulating layer and into the plurality of individual openings over the first interconnect structure.
14. The semiconductor device of claim 13 , wherein a pitch of the individual openings is 40 micrometers.
15. The semiconductor device of claim 13 , wherein the individual openings include a circular shape, ring shape, cross shape, or lattice shape.
16. The semiconductor device of claim 13 , further including a second insulating layer formed over the conductive layer and first insulating layer.
17. The semiconductor device of claim 16 , wherein the second insulating layer includes a thickness of less than 25 micrometers.
18. The semiconductor device of claim 13 , further including
an encapsulant formed over the semiconductor die and interconnect structure with
an opening formed in the encapsulant over the interconnect structure.
19. A semiconductor device, comprising:
a semiconductor die;
an interconnect unit disposed in a peripheral region of the semiconductor die, wherein the interconnect unit includes a conductive via formed through the interconnect unit; and
a first insulating layer formed over the semiconductor die and interconnect unit including a first opening of the first insulating layer formed over a first portion of the conductive via and a second opening of the first insulating layer formed over a second portion of the conductive via, wherein the first opening and second opening extend to a surface of the conductive via leaving a portion of the first insulating layer around the first opening and second opening over the surface of the conductive via.
20. The semiconductor device of claim 19 , wherein a pitch of the first opening and second opening is 40 micrometers.
21. The semiconductor device of claim 19 , wherein the first opening and second opening include a circular shape, ring shape, cross shape, or lattice shape.
22. The semiconductor device of claim 19 , further including:
a conductive layer formed over the first insulating layer and into the first opening and second opening over the conductive via; and
a second insulating layer formed over the conductive layer and first insulating layer.
23. The semiconductor device of claim 22 , wherein a surface of the conductive layer is planar.