IP Library Granted Patent US 8,890,315
Granted Patent B2
US 8,890,315 · App. 14/021,056 · Granted Nov 18, 2014

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

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Quick Facts
Patent No.
US 8,890,315
App. No.
14/021,056
Granted
Nov 18, 2014
Kind
B2
Abstract

A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Claims (36)

1. A semiconductor device, comprising:

a substrate;

an insulating layer formed over the substrate;

a first conductive layer formed into an opening of the insulating layer; and

an interconnect structure extending from the substrate through the opening in the insulating layer covering the first conductive layer, wherein a portion of the interconnect structure includes a width less than the opening in the insulating layer.

2. The semiconductor device of claim 1 , further including a second conductive layer formed over the substrate.

3. The semiconductor device of claim 1 , wherein the interconnect structure includes a conductive pillar.

4. The semiconductor device of claim 1 , wherein the interconnect structure includes a first conductive pad.

5. The semiconductor device of claim 4 , wherein the interconnect structure further includes a second conductive pad formed over the first conductive pad.

6. The semiconductor device of claim 4 , wherein the interconnect structure further includes a bump material deposited over the first conductive pad.

7. A semiconductor device, comprising:

a substrate including an insulating layer disposed over the substrate;

a first conductive layer formed in an opening of the insulating layer; and

an interconnect structure including a first width within the opening and below a surface of the insulating layer and a second width less than the first width outside the opening of the insulating layer.

8. The semiconductor device of claim 7 , further including a second conductive layer formed over the substrate.

9. The semiconductor device of claim 7 , wherein the interconnect structure includes a conductive pillar.

10. The semiconductor device of claim 7 , wherein the interconnect structure includes a first conductive pad.

11. The semiconductor device of claim 10 , wherein the interconnect structure further includes a bump material deposited over the first conductive pad.

12. The semiconductor device of claim 10 , wherein the interconnect structure further includes a second conductive pad formed over the first conductive pad.

13. The semiconductor device of claim 12 , wherein the second conductive pad is disposed around a perimeter of the first conductive pad or in an interior region of the first conductive pad.

14. A semiconductor device, comprising:

a substrate including an insulating layer disposed over the substrate; and

an interconnect structure including a first width within an opening in the insulating layer and a second width less than the opening of the insulating layer.

15. The semiconductor device of claim 14 , further including a conductive layer formed in the opening of the insulating layer.

16. The semiconductor device of claim 14 , wherein the interconnect structure includes a conductive pillar.

17. The semiconductor device of claim 14 , wherein the interconnect structure includes a first conductive pad.

18. The semiconductor device of claim 17 , wherein the interconnect structure further includes a second conductive pad formed over the first conductive pad.

19. The semiconductor device of claim 17 , wherein the interconnect structure further includes a bump material deposited over the first conductive pad.

20. A semiconductor device, comprising:

a substrate including an insulating layer disposed over the substrate; and

an interconnect structure extending from the substrate through an opening in the insulating layer, wherein the interconnect structure includes a width less than the opening of the insulating layer.

21. The semiconductor device of claim 20 , further including a conductive layer formed in the opening of the insulating layer.

22. The semiconductor device of claim 20 , wherein the interconnect structure includes a conductive pillar.

23. The semiconductor device of claim 20 , wherein the interconnect structure includes a first conductive pad.

24. The semiconductor device of claim 23 , wherein the interconnect structure further includes a second conductive pad formed over the first conductive pad.

25. The semiconductor device of claim 23 , wherein the interconnect structure further includes a bump material deposited over the first conductive pad.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE. " TO STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0391. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064809/0877 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF THE ASSIGNEE'S NAME ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0161. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064805/0735 →
RELEASE OF SECURITY INTEREST Recorded Jun 16, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052963/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0360 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0161 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0391 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →