Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
View Patent ↗A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable.
1. A method of making a semiconductor device, comprising:
providing a substrate;
disposing a first semiconductor die over a first surface of the substrate;
forming a first interconnect structure over the first surface of the substrate outside of a first footprint of the first semiconductor die;
depositing a first encapsulant over the first semiconductor die and first interconnect structure and a side surface of the substrate;
disposing a second semiconductor die over a second surface of the substrate opposite the first surface; and
forming a second interconnect structure over the second surface of the substrate.
2. The method of claim 1 , further including forming the second interconnect structure outside a second footprint of the second semiconductor die.
3. The method of claim 2 , further including depositing a second encapsulant over the second semiconductor die, the second interconnect structure exposed with respect to the second encapsulant.
4. The method of claim 1 , further including forming a conductive via through the substrate.
5. The method of claim 1 , wherein the first semiconductor die includes an active surface oriented toward the first surface of the substrate and the second semiconductor die includes an active surface oriented toward the second surface of the substrate.
6. A method of making a semiconductor device, comprising:
providing a substrate;
disposing a first semiconductor die over a first surface of the substrate;
depositing a first encapsulant over the first semiconductor die and a side surface of the substrate; and
disposing a second semiconductor die over a second surface of the substrate opposite the first surface.
7. The method of claim 6 , further including forming an interconnect structure over the first surface of the substrate prior to depositing the first encapsulant.
8. The method of claim 7 , further including depositing the first encapsulant to partially expose the interconnect structure.
9. The method of claim 6 , further including depositing a second encapsulant over the second semiconductor die.
10. The method of claim 6 , further including forming an interconnect structure over the second surface of the substrate outside a footprint of the second semiconductor die.
11. The method of claim 6 , further including forming a shielding layer over the first semiconductor die and first encapsulant.
12. The method of claim 6 , further including forming a conductive via through the substrate.
13. A semiconductor device, comprising:
a substrate;
a first semiconductor die disposed over a first surface of the substrate;
a first encapsulant deposited over the first semiconductor die and a side surface of the substrate; and
a second semiconductor die disposed over a second surface of the substrate.
14. The semiconductor device of claim 13 , further including an interconnect structure formed over the second surface of the substrate outside a footprint of the second semiconductor die.
15. The semiconductor device of claim 14 , further including a second encapsulant deposited over the second semiconductor die, wherein the interconnect structure is exposed from the second encapsulant.
16. The semiconductor device of claim 14 , further including a plurality of semiconductor devices stacked and electrically connected through the interconnect structure.
17. The semiconductor device of claim 13 , further including an interconnect structure formed over the first surface of the substrate outside a footprint of the first semiconductor die, the interconnect structure partially exposed from the first encapsulant.
18. The semiconductor device of claim 13 , wherein the first semiconductor die includes an active surface oriented toward the first surface of the substrate and the second semiconductor die includes an active surface oriented toward the second surface of the substrate.
19. The semiconductor device of claim 13 , further including a conductive via formed through the substrate.
20. A semiconductor device, comprising:
a substrate;
a first semiconductor die disposed over the substrate, wherein the substrate includes a coefficient of thermal expansion (CTE) that matches a CTE of a base material of the first semiconductor die;
an interconnect structure formed over the substrate; and
a first encapsulant deposited over the first semiconductor die, over a side surface of the substrate, and around the interconnect structure.
21. The semiconductor device of claim 20 , wherein the interconnect structure is partially exposed from the first encapsulant.
22. The semiconductor device of claim 20 , further including the interconnect structure formed outside a footprint of the first semiconductor die and electrically connected to the first semiconductor die through the substrate.
23. The semiconductor device of claim 20 , further including a second semiconductor die disposed over the substrate opposite the first semiconductor die.
24. The semiconductor device of claim 20 , further including a plurality of semiconductor devices stacked and electrically connected through the interconnect structure.