Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
View Patent ↗A semiconductor device has a first semiconductor die mounted over a carrier. Wettable contact pads can be formed over the carrier. A second semiconductor die is mounted over the first semiconductor die. The second die is laterally offset with respect to the first die. An electrical interconnect is formed between an overlapping portion of the first die and second die. A plurality of first conductive pillars is disposed over the first die. A plurality of second conductive pillars is disposed over the second die. An encapsulant is deposited over the first and second die and first and second conductive pillars. A first interconnect structure is formed over the encapsulant, first conductive pillars, and second die. The carrier is removed. A second interconnect structure is formed over the encapsulant, second conductive pillars, and first die. A third conductive pillar is formed between the first and second build-up interconnect structures.
1. A semiconductor device, comprising:
a first semiconductor die;
a second semiconductor die disposed over a portion of the first semiconductor die and laterally offset from the first semiconductor die;
a plurality of first conductive pillars disposed over the first semiconductor die;
an encapsulant deposited over the first semiconductor die;
an insulating layer formed on the encapsulant; and
an electrical interconnect formed between the portion of the first semiconductor die and the second semiconductor die.
2. The semiconductor device of claim 1 , wherein the electrical interconnect includes a bump, stud bump, or second conductive pillar.
3. The semiconductor device of claim 1 , further including a plurality of second conductive pillars disposed around the first semiconductor die or second semiconductor die.
4. The semiconductor device of claim 1 , further including an interconnect structure formed over the encapsulant and electrically connected to the first conductive pillars.
5. The semiconductor device of claim 1 , further including a third semiconductor die disposed over the first semiconductor die or second semiconductor die and laterally offset with respect to the first semiconductor die or second semiconductor die.
6. A semiconductor device, comprising:
a first semiconductor die;
a second semiconductor die disposed over and laterally offset from the first semiconductor die; and
a plurality of first conductive pillars disposed over the first semiconductor die and outside a footprint of the second semiconductor die.
7. The semiconductor device of claim 6 , further including an encapsulant deposited around the first semiconductor die and second semiconductor die.
8. The semiconductor device of claim 7 , further including an interconnect structure formed over the encapsulant and electrically connected to the first conductive pillars.
9. The semiconductor device of claim 6 , further including an electrical interconnect formed between the first semiconductor die and second semiconductor die.
10. The semiconductor device of claim 6 , further including a plurality of second conductive pillars disposed around the first semiconductor die or second semiconductor die.
11. The semiconductor device of claim 6 , further including a plurality of conductive vias formed through the first semiconductor die or second semiconductor die.
12. The semiconductor device of claim 6 , further including a third semiconductor die disposed over the first semiconductor die or second semiconductor die and laterally offset with respect to the first semiconductor die or second semiconductor die.
13. A semiconductor device, comprising:
a first semiconductor die;
a second semiconductor die disposed over and laterally offset from the first semiconductor die;
a third semiconductor die disposed over the first semiconductor die and laterally offset from the first and second semiconductor dies;
a first interconnect structure disposed over the first semiconductor die or second semiconductor die; and
an encapsulant deposited around the first semiconductor die, second semiconductor die, and first interconnect structure.
14. The semiconductor device of claim 13 , wherein the first interconnect structure includes a plurality of conductive pillars disposed over the first semiconductor die and outside a footprint of the second semiconductor die.
15. The semiconductor device of claim 13 , further including a plurality of semiconductor devices electrically connected through the first interconnect structure.
16. The semiconductor device of claim 13 , further including an electrical interconnect formed between the first semiconductor die and second semiconductor die.
17. The semiconductor device of claim 13 , further including a plurality of conductive pillars disposed around the first semiconductor die or second semiconductor die.
18. The semiconductor device of claim 13 , further including a second interconnect structure formed over the encapsulant and electrically connected to the first interconnect structure.
19. The semiconductor device of claim 13 , further including a plurality of conductive vias formed through the first semiconductor die or second semiconductor die.
20. A semiconductor device, comprising:
a first semiconductor die;
a second semiconductor die disposed over and laterally offset from the first semiconductor die;
a first interconnect structure disposed over the first semiconductor die or second semiconductor die; and
a second interconnect structure formed outside a footprint of the first and second semiconductor dies.
21. The semiconductor device of claim 20 , wherein the first interconnect structure includes a plurality of conductive pillars disposed over the first semiconductor die or second semiconductor die.
22. The semiconductor device of claim 20 , further including an encapsulant deposited around the first semiconductor die, second semiconductor die, and first interconnect structure.
23. The semiconductor device of claim 22 , further including a third interconnect structure disposed over the encapsulant and electrically connected to the first interconnect structure.
24. The semiconductor device of claim 20 , further including an electrical interconnect formed between the first semiconductor die and second semiconductor die.