IP Library Granted Patent US 9,818,835
Granted Patent B2
US 9,818,835 · App. 15/234,775 · Granted Nov 14, 2017

Semiconductor device

Inventors: Saichirou Kaneko (Kyoto, JP); Hiroto Yamagiwa (Hyogo, JP); Ayanori Ikoshi (Kyoto, JP); Masayuki Kuroda (Osaka, JP); Manabu Yanagihara (Osaka, JP); Kenichiro Tanaka (Osaka, JP); Tetsuyuki Fukushima (Hyogo, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L29/475H01L21/28H01L29/0619H01L29/1029H01L29/2003H01L29/205H01L29/7786H01L29/7787H01L29/872H01L29/1066H01L29/42316
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Quick Facts
Patent No.
US 9,818,835
App. No.
15/234,775
Granted
Nov 14, 2017
Kind
B2
Abstract

In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

Claims (69)

1. A semiconductor device comprising:

a substrate;

a first nitride semiconductor layer provided on the substrate;

a second nitride semiconductor layer provided on the first nitride semiconductor layer;

a first electrode provided above a lower surface of the first nitride semiconductor layer and serving as a source electrode or an anode electrode;

a second electrode provided above the lower surface of the first semiconductor layer and serving as a drain electrode or a cathode electrode; and

an electrode portion provided above a lower surface of the second nitride semiconductor layer, wherein:

the first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with the second nitride semiconductor layer,

the first nitride semiconductor layer and the second nitride semiconductor layer form a semiconductor layer stacked body,

the electrode portion is disposed between the first electrode and the second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than a space between the first electrode and the electrode portion, in plan view,

a junction surface between the electrode portion and the second nitride semiconductor layer has an energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer,

a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer,

the electrode portion has a potential substantially equal to a potential of the second electrode,

the two-dimensional electron gas channel under the electrode portion is in a conductive state between the first electrode and the second electrode, when a maximum operating voltage, which renders the first electrode positive with respect to the second electrode, is applied between the first electrode and the second electrode,

an interlayer insulating film is formed to cover the second electrode,

the interlayer insulating film partially has an opening over a part of the second electrode,

a second electrode wiring is formed in the opening and connected to the second electrode, and

an edge of the second electrode wiring on a first electrode side is disposed over the interlayer insulating film and is located at a substantially same position of an edge of the electrode portion on a first electrode side, in plan view, or the edge of the second electrode wiring on the first electrode side is located at a position closer to the second electrode than the edge of the electrode portion on the first electrode side, in plan view.

2. The semiconductor device according to claim 1 , wherein:

the second electrode is surrounded by the electrode portion, and

the opening is disposed at an intersecting point between the second electrode wiring and the electrode portion.

3. The semiconductor device according to claim 1 , wherein

the electrode portion forms a Schottky contact with second nitride semiconductor layer.

4. The semiconductor device according to claim 1 , further comprising a gate electrode formed on the semiconductor layer stacked body and between the first electrode and the electrode portion with a space between the first electrode and the electrode portion, wherein:

the first electrode is a source electrode,

the second electrode is a drain electrode, and

the semiconductor device functions as a field effect transistor.

5. The semiconductor device according to claim 4 , wherein

when a second voltage lower than a breakdown voltage of the semiconductor device is applied to a place between the source electrode and the drain electrode with a first voltage equal to or higher than a gate threshold voltage being applied to the gate electrode, a potential difference between the electrode portion and the second nitride semiconductor layer just under the electrode portion reaches a value equal to or greater than the energy barrier, and a current flows from the electrode portion to the source electrode.

6. The semiconductor device according claim 2 , further comprising a gate electrode formed on the semiconductor layer stacked body and between the first electrode and the electrode portion with a space between the first electrode and the electrode portion, wherein:

the first electrode is a source electrode,

the second electrode is a drain electrode, and

the semiconductor device functions as a field effect transistor.

7. The semiconductor device according to claim 6 , wherein

when a second voltage lower than a breakdown voltage of the semiconductor device is applied to a place between the source electrode and the drain electrode with a first voltage equal to or higher than a gate threshold voltage being applied to the gate electrode, a potential difference between the electrode portion and the second nitride semiconductor layer just under the electrode portion reaches a value equal to or greater than the energy barrier, and a current flows from the electrode portion to the source electrode.

8. The semiconductor device according claim 3 , further comprising a gate electrode formed on the semiconductor layer stacked body and between the first electrode and the electrode portion with a space between the first electrode and the electrode portion, wherein:

the first electrode is a source electrode,

the second electrode is a drain electrode, and

the semiconductor device functions as a field effect transistor.

9. The semiconductor device according to claim 8 , wherein

when a second voltage lower than a breakdown voltage of the semiconductor device is applied to a place between the source electrode and the drain electrode with a first voltage equal to or higher than a gate threshold voltage being applied to the gate electrode, a potential difference between the electrode portion and the second nitride semiconductor layer just under the electrode portion reaches a value equal to or greater than the energy barrier, and a current flows from the electrode portion to the source electrode.

10. A semiconductor device comprising:

a substrate;

a first nitride semiconductor layer provided on the substrate;

a second nitride semiconductor layer provided on the first nitride semiconductor layer;

a first electrode provided above a lower surface of the first nitride semiconductor layer and serving as a source electrode or an anode electrode;

a second electrode provided above the lower surface of the first semiconductor layer and serving as a drain electrode or a cathode electrode; and

an electrode portion provided above a lower surface of the second nitride semiconductor layer, wherein:

the first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with the second nitride semiconductor layer,

the first nitride semiconductor layer and the second nitride semiconductor layer form a semiconductor layer stacked body,

the electrode portion is disposed between the first electrode and the second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than a space between the first electrode and the electrode portion, in plan view,

a junction surface between the electrode portion and the second nitride semiconductor layer has an energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer,

a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer,

the electrode portion has a potential substantially equal to a potential of the second electrode,

the two-dimensional electron gas channel under the electrode portion is in a conductive state between the first electrode and the second electrode, when a maximum operating voltage, which renders the first electrode positive with respect to the second electrode, is applied between the first electrode and the second electrode,

an interlayer insulating film is formed to cover the second electrode,

the interlayer insulating film partially has an opening over a part of the second electrode,

a second electrode wiring is formed in the opening and connected to the second electrode,

an edge of the second electrode wiring on a first electrode side is disposed over the interlayer insulating film and is located at a substantially same position of an edge of the electrode portion on a first electrode side, in plan view, or the edge of the second electrode wiring on the first electrode side is located at a position closer to the second electrode than the edge of the electrode portion on the first electrode side, in plan view,

the second electrode is surrounded by the electrode portion, and

the opening is disposed at an intersecting point between the second electrode wiring and the electrode portion, and

the electrode portion forms a Schottky contact with second nitride semiconductor layer.

11. The semiconductor device according to claim 1 , wherein the edge of the second electrode wiring on the first electrode side is located between the edge of the electrode portion on the first electrode side and an edge of the second electrode on a first electrode side, in plan view.

12. The semiconductor device according to claim 1 , wherein a width of the second electrode wiring in a direction of the first electrode and the second electrode is greater than a width of the second electrode in a direction of the first electrode and the second electrode.

13. The semiconductor device according to claim 10 , wherein the edge of the second electrode wiring on the first electrode side is located between the edge of the electrode portion on the first electrode side and an edge of the second electrode on a first electrode side, in plan view.

14. The semiconductor device according to claim 10 , wherein a width of the second electrode wiring in a direction of the first electrode and the second electrode is greater than a width of the second electrode in a direction of the first electrode and the second electrode.

15. The semiconductor device according to claim 4 , wherein:

under a forward bias condition, in which the drain electrode is positively biased with respect to the source electrode, a current flows from the drain electrode to the source electrode, and

under a reverse bias condition, in which the source electrode is positively biased with respect to the drain electrode, a current flows from the source electrode to the drain electrode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2025
From: INFINEON TECHNOLOGIES AUSTRIA AG
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 072853/0508 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2024
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 069503/0625 →
Priority Claims (1)
JP 2013-092347 · Apr 25, 2013 · national
Continuity (3)
Division 14884815 · Oct 16, 2015
Continuation PCTJP2014002184 · Apr 17, 2014
Related Publication 20160351676A1 · Dec 1, 2016