IP Library Granted Patent US 9,641,190
Granted Patent B1
US 9,641,190 · App. 15/267,356 · Granted May 2, 2017

Continuous-time cascaded sigma-delta analog-to-digital converter

Inventors: Brandt Braswell (Chandler, AZ); George Kunnen (Chandler, AZ)
Assignee: NXP USA, INC.
H03M1/1245H03M3/422H03M3/436H03M3/464
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Quick Facts
Patent No.
US 9,641,190
App. No.
15/267,356
Granted
May 2, 2017
Kind
B1
Abstract

A multi-rate cascaded continuous-time analog-to-digital converter has a plurality of sigma-delta modulator stages and includes first and second continuous-time sigma-delta modulators, and a summation element. The first continuous-time sigma-delta modulator operates at a first sampling rate. The second continuous-time sigma-delta modulator operates at a second sampling rate higher than the first sampling rate. The second continuous-time sigma-delta modulator has a continuous-time voltage controlled oscillator (VCO) quantizer, and a feedback loop coupled between the input and the output. The second continuous-time sigma-delta modulator is cascaded with the first continuous-time sigma-delta modulator. The summation element has inputs coupled to outputs of the first and second continuous-time sigma-delta modulators.

Claims (64)

1. A multi-rate cascaded continuous-time analog-to-digital converter comprising:

at least one first continuous-time sigma-delta modulator configured to operate at a first sampling rate, each of the at least one first continuous-time sigma-delta modulators having an input, an output, and a feedback loop coupled between the input and the output;

a second continuous-time sigma-delta modulator configured to operate at a second sampling rate higher than the first sampling rate, the second continuous-time sigma-delta modulator having an input, an output, a continuous-time voltage controlled oscillator (VCO) quantizer, and a feedback loop coupled between the input and the output, wherein the second continuous-time sigma-delta modulator is cascaded with the at least one continuous-time sigma-delta modulator; and

a summation element having inputs coupled to the outputs of the at least one first continuous-time sigma-delta modulator and the second continuous-time sigma-delta modulator, and an output.

2. The multi-rate cascaded continuous-time analog-to-digital converter of claim 1 ,

wherein the at least one first continuous-time sigma-delta modulator comprises:

a difference element having a first input coupled to receive an analog input signal, a second input coupled to receive a feedback signal, and an output;

a loop filter coupled to the output of the difference element;

a quantizer coupled to the loop filter;

a feedback loop coupled between an output of the quantizer and the second input of the first difference element for providing the feedback signal; and

digital logic coupled to the output of the quantizer for providing a digital signal.

3. The multi-rate cascaded continuous-time analog-to-digital converter of claim 2 , wherein the quantizer is a 1-bit quantizer.

4. The multi-rate cascaded continuous-time analog-to-digital converter of claim 2 , wherein the digital logic operates at the second sampling rate.

5. The multi-rate cascaded continuous-time analog-to-digital converter of claim 2 , wherein the digital logic receives a control signal for tuning a transfer function of the digital logic.

6. The multi-rate cascaded continuous-time analog-to-digital converter of claim 1 , wherein the feedback loops of the at least one first continuous-time sigma-delta modulator and the second continuous-time sigma-delta modulator comprises a digital-to-analog converter.

7. The multi-rate cascaded continuous-time analog-to-digital converter of claim 1 ,

wherein the second continuous-time sigma-delta modulator comprises:

a difference element having a first input coupled to the output of the at least one first continuous-time sigma-delta modulator, a second input coupled to receive a feedback signal, and an output;

a continuous-time voltage controlled oscillator (VCO) quantizer;

a feedback loop coupled between an output of the VCO quantizer and the second input of the difference element for providing the feedback signal; and

digital logic coupled to the output of the VCO quantizer for providing a digital signal.

8. The multi-rate cascaded continuous-time analog-to-digital converter of claim 7 , wherein the digital logic operates at the second sampling rate.

9. The multi-rate cascaded continuous-time analog-to-digital converter of claim 7 , wherein the digital logic receives a control signal for tuning a transfer function of the digital logic.

10. The multi-rate cascaded continuous-time analog-to-digital converter of claim 1 , wherein the second sampling rate is an integer multiple of the first sampling rate.

11. The multi-rate cascaded continuous-time analog-to-digital converter of claim 1 , wherein a first continuous-time sigma-delta modulator of the at least one first continuous-time sigma-delta modulator is a second order continuous-time sigma-delta modulator, and the second continuous-time sigma-delta modulator is a first order continuous-time sigma-delta modulator.

12. A multi-rate cascaded continuous-time analog-to-digital converter comprising:

a first continuous-time sigma-delta modulator configured to operate at a first sampling rate, the first continuous-time sigma-delta modulator comprising:

a first difference element having a first input coupled to receive an analog input signal, a second input coupled to receive a first feedback signal, and an output;

a first loop filter coupled to the output of the difference element;

a first quantizer coupled to the first loop filter;

a first feedback loop coupled between an output of the first quantizer and the second input of the first difference element for providing the first feedback signal; and

first digital logic coupled to the output of the first quantizer for providing a first digital signal;

a second continuous-time sigma-delta modulator configured to operate at a second sampling rate higher than the first sampling rate, the second continuous-time sigma-delta modulator comprising:

a second difference element having a first input coupled to an output of the first loop filter, a second input coupled to receive a second feedback signal, and an output;

a continuous-time voltage controlled oscillator (VCO) quantizer;

a second feedback loop coupled between an output of the VCO quantizer and the second input of the second difference element for providing the second feedback signal; and

second digital logic coupled to the output of the VCO quantizer for providing a second digital signal; and

a summation element having a first input coupled to the first digital logic for receiving the first digital signal, and a second input coupled to the second digital logic for receiving the second digital signal, and an output for providing a digital output signal.

13. The multi-rate cascaded continuous-time analog-to-digital converter of claim 12 , wherein the second sampling rate is an integer multiple of the first sampling rate.

14. The multi-rate cascaded continuous-time analog-to-digital converter of claim 12 , wherein the first and second digital logic both operate at the second sampling rate.

15. The multi-rate cascaded continuous-time analog-to-digital converter of claim 12 , wherein the first and second digital logic each receives a control signal for tuning a transfer function of the digital logic.

16. The multi-rate cascaded continuous-time analog-to-digital converter of claim 12 , wherein the first continuous-time sigma-delta modulator is a second order continuous-time sigma-delta modulator, and the second continuous-time sigma-delta modulator is a first order continuous-time sigma-delta modulator.

17. A multi-rate cascaded continuous-time analog-to-digital converter comprising:

a first continuous-time sigma-delta modulator configured to operate at a first sampling rate, the first continuous-time sigma-delta modulator comprising:

a first difference element having a first input coupled to receive an analog input signal, a second input coupled to receive a first feedback signal, and an output;

a first loop filter coupled to the output of the difference element;

a first quantizer coupled to the first loop filter;

a first feedback loop coupled between an output of the first quantizer and the second input of the first difference element for providing the first feedback signal; and

first digital logic coupled to the output of the quantizer for providing a first digital signal;

a second continuous-time sigma-delta modulator configured to operate at a second sampling rate, the second sampling rate being greater than or equal to the first sampling rate, the second continuous-time sigma-delta modulator comprising:

a second difference element having a first input coupled to receive an analog input signal, a second input coupled to receive a second feedback signal, and an output;

a second loop filter coupled to the output of the difference element;

a second quantizer coupled to the second loop filter;

a second feedback loop coupled between an output of the second quantizer and the second input of the second difference element for providing the second feedback signal; and

second digital logic coupled to the output of the second quantizer for providing a second digital signal;

a third continuous-time sigma-delta modulator configured to operate at a third sampling rate higher than the first and second sampling rates, the third continuous-time sigma-delta modulator comprising:

a third difference element having a first input coupled to an output of the second loop filter, a second input coupled to receive a third feedback signal, and an output;

a continuous-time voltage controlled oscillator (VCO) quantizer;

a third feedback loop coupled between an output of the VCO quantizer and the second input of the third difference element for providing the third feedback signal; and

third digital logic coupled to the output of the VCO quantizer for providing a third digital signal; and

a summation element having a first input coupled to the first digital logic for receiving the first digital signal, a second input coupled to the second digital logic for receiving the second digital signal, a third input coupled to the third digital logic for receiving the third digital signal, and an output for providing a digital output signal.

18. The multi-rate cascaded continuous-time analog-to-digital converter of claim 17 , wherein the first continuous-time sigma-delta modulator is a second order continuous-time sigma-delta modulator, the second continuous-time sigma-delta modulator is a first order continuous-time sigma-delta modulator, and the third continuous-time sigma-delta modulator is a first order continuous-time sigma-delta modulator.

19. The multi-rate cascaded continuous-time analog-to-digital converter of claim 17 , wherein the first, second, and third digital logic operate at the third sampling rate.

20. The multi-rate cascaded continuous-time analog-to-digital converter of claim 17 , wherein the first, second, and third digital logic each receives a control signal for tuning a transfer function of the first, second, and third digital logic.

Assignments (2)
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2016
From: BRASWELL, BRANDT; KUNNEN, GEORGE
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 039764/0319 →