IE type trench gate IGBT
In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.
1. A semiconductor device comprising:
(a) a semiconductor substrate having first and second main surfaces;
(b) a drift area disposed in the semiconductor substrate and having a first conductive type;
(c) first and second cells arranged in a first direction on the first main surface, and extending along a second direction which is perpendicular to the first direction;
(d) a metal gate electrode disposed over the first main surface; and
(e) a metal emitter electrode disposed over the first main surface;
the first cell including:
first and second gate electrodes disposed in first and second trenches in the first main surface, respectively, and connected electrically to the metal gate electrode,
wherein the first and second gate electrodes are arranged in the first direction and extend along the second direction;
a first semiconductor region disposed between the first and second trenches over the drift area and having a second conductive type opposite to the first conductive type;
second semiconductor regions having the second conductive type disposed at both sides of the first and second gate electrodes; and
a third semiconductor region having the first conductive type disposed on the first semiconductor region;
the second cell including:
third and fourth gate electrodes disposed in third and fourth trenches in the first main surface, respectively, and connected electrically to the metal emitter electrode,
wherein the third and fourth gate electrodes are arranged in the first direction and extend along the second direction;
a fourth semiconductor region disposed between the third and fourth trenches over the drift area and having the second conductive type; and
fifth semiconductor regions having the second conductive type disposed at both sides of the third and fourth gate electrodes;
wherein a depth of the second semiconductor region adjacent to the first trench is deeper than a lower end of the first trench.
2. The semiconductor device according to claim 1 ,
wherein a width between the first and second trenches is narrower than a width of the second and third trenches.
3. The semiconductor device according to claim 1 ,
wherein the third semiconductor region is not disposed between the third and fourth trenches.
4. The semiconductor device according to claim 1 , further comprising:
an insulating film disposed between the fourth semiconductor region and the metal emitter electrode,
wherein the fourth semiconductor region contacts the insulating film.
5. The semiconductor device according to claim 1 ,
wherein a width between the first and second trenches is substantially equal to a width between the third and fourth trenches.
6. The semiconductor device according to claim 1 , further comprising:
a sixth semiconductor region having the first conductive type disposed between the first and second trenches and on the first semiconductor region,
wherein the sixth semiconductor region is apart from the third semiconductor region in the second direction.
7. The semiconductor device according to claim 1 , further comprising:
first connection parts extending along the first direction and connecting the third gate electrodes to the fourth gate electrodes,
wherein the first connection parts are connected to the metal emitter electrode.