Semiconductor device and fabrication method for the same
The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
1. A semiconductor device comprising:
a gate electrode formed on an active region of a semiconductor substrate;
a first silicon-germanium layer formed in a first depression provided in a portion of the active region;
the first silicon-germanium layer comprising silicon and germanium;
a gate interconnect formed at a position opposite to the gate electrode with respect to the first depression;
a first contact plug comprised of tungsten;
a first sidewall formed on the side face of the gate interconnect closer to the first depression;
a second sidewall formed on the other side face of the gate interconnect;
the bottom surface of the first contact plug is not lower than the bottom surface of the first sidewall and the bottom surface of the first contact plug is not lower than the bottom surface of the second sidewall;
wherein, in a cross-sectional configuration, the first sidewall is lower in height than the second sidewall, the gate interconnect is formed at least partly on the active region, and the first contact plug is electrically connected to the first silicon-germanium layer and the gate interconnect.
2. The semiconductor device of claim 1 , wherein, in the cross-sectional configuration, at least a portion of the first silicon-germanium layer protrudes above the top surface of the semiconductor substrate.
3. The semiconductor device of claim 2 , wherein the first contact plug does not contact the second sidewall.
4. The semiconductor device of claim 1 , further comprising:
a first portion of a silicide layer is formed on the first silicon-germanium layer;
wherein, in the cross-sectional configuration, the first portion of the silicide layer electrically connects the first contact plug and the first silicon-germanium layer.
5. The semiconductor device of claim 2 , further comprising:
a first portion of a silicide layer is formed on the first silicon-germanium layer;
wherein, in the cross-sectional configuration, the first portion of the silicide layer electrically connects the first contact plug and the first silicon-germanium layer.
6. The semiconductor device of claim 5 , wherein the silicide layer is comprised of nickel.
7. The semiconductor device of claim 6 , wherein the first contact plug does not contact the second sidewall.
8. The semiconductor device of claim 5 , wherein the first contact plug does not contact the second sidewall.
9. The semiconductor device of claim 4 , wherein, in the cross-sectional configuration, at least a portion of the first portion of the silicide layer protrudes above the top surface of the semiconductor substrate.
10. The semiconductor device of claim 9 , wherein the silicide layer is comprised of nickel.
11. The semiconductor device of claim 10 , wherein the first contact plug does not contact the second sidewall.
12. The semiconductor device of claim 9 , wherein the first contact plug does not contact the second sidewall.
13. The semiconductor device of claim 4 , wherein the silicide layer is comprised of nickel.
14. The semiconductor device of claim 13 , wherein the first contact plug does not contact the second sidewall.
15. The semiconductor device of claim 4 , wherein the first contact plug does not contact the second sidewall.
16. The semiconductor device of claim 1 , wherein the first contact plug does not contact the second sidewall.
17. The semiconductor device of claim 1 , wherein, in the cross-sectional configuration, the gate interconnect is formed entirely on the active region.
18. The semiconductor device of claim 1 , wherein the first silicon-germanium layer is an epitaxial layer.
19. The semiconductor device of claim 1 , wherein:
the gate interconnect has a long axis extending along the semiconductor substrate in a direction perpendicular to the gate length direction;
a first portion of the first sidewall extends under the entire first contact plug in the direction of the long axis of the gate interconnect; and
the first portion of the first sidewall is continuous in the direction of the long axis of the gate interconnect.
20. A semiconductor device comprising:
a gate electrode formed on an active region of a semiconductor substrate;
a first silicon-germanium layer formed in a first depression provided in a portion of the active region;
the first silicon-germanium layer comprised of silicon and germanium;
a gate interconnect formed at a position opposite to the gate electrode with respect to the first depression;
a first contact plug comprised of tungsten;
a first sidewall formed on the side face of the gate interconnect closer to the first depression;
a second sidewall formed on the other side face of the gate interconnect;
the bottom surface of the first contact plug is not lower than the bottom surface of the first sidewall and the bottom surface of the first contact plug is not lower than the bottom surface of the second sidewall;
wherein, in a cross-sectional configuration, the first sidewall is lower in height than the second sidewall, and the first contact plug is electrically connected to the first silicon-germanium layer and the gate interconnect.
21. The semiconductor device of claim 20 , wherein, in the cross-sectional configuration, at least a portion of the first silicon-germanium layer protrudes above the top surface of the semiconductor substrate.
22. The semiconductor device of claim 21 , further comprising:
a first portion of a silicide layer is formed on the first silicon-germanium layer;
wherein, in the cross-sectional configuration, the first portion of the silicide layer electrically connects the first contact plug and the first silicon-germanium layer.
23. The semiconductor device of claim 22 , wherein the silicide layer is comprised of nickel.
24. The semiconductor device of claim 23 , wherein the first contact plug does not contact the second sidewall.
25. The semiconductor device of claim 22 , wherein the first contact plug does not contact the second sidewall.
26. The semiconductor device of claim 21 , wherein the first contact plug does not contact the second sidewall.
27. The semiconductor device of claim 20 , further comprising:
a first portion of a silicide layer is formed on the first silicon-germanium layer;
wherein, in the cross-sectional configuration, the first portion of the silicide layer electrically connects the first contact plug and the first silicon-germanium layer.
28. The semiconductor device of claim 27 , wherein, in the cross-sectional configuration, at least a portion of the first portion of the silicide layer protrudes above the top surface of the semiconductor substrate.
29. The semiconductor device of claim 28 , wherein the silicide layer is comprised of nickel.
30. The semiconductor device of claim 29 , wherein the first contact plug does not contact the second sidewall.
31. The semiconductor device of claim 28 , wherein the first contact plug does not contact the second sidewall.
32. The semiconductor device of claim 27 , wherein the silicide layer is comprised of nickel.
33. The semiconductor device of claim 32 , wherein the first contact plug does not contact the second sidewall.
34. The semiconductor device of claim 27 , wherein the first contact plug does not contact the second sidewall.
35. The semiconductor device of claim 20 , wherein the first contact plug does not contact the second sidewall.
36. The semiconductor device of claim 20 , wherein the first silicon-germanium layer is an epitaxial layer.
37. The semiconductor device of claim 20 , wherein:
the gate interconnect has a long axis extending along the semiconductor substrate in a direction perpendicular to the gate length direction;
a first portion of the first sidewall extends under the entire first contact plug in the direction of the long axis of the gate interconnect; and
the first portion of the first sidewall is continuous in the direction of the long axis of the gate interconnect.