SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE
Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.
1 . A controller for controlling operation of a memory device, the controller comprising:
a verification signal generation circuit configured to:
generate a verification signal PRTY based on an address signal ADD and a command signal CMD; and
an output circuit configured to:
supply a chip select signal CS, the address signal ADD, the command signal CMD and the verification signal PRTY to the memory device.
2 . The controller of claim 1 , wherein the memory device is a DRAM.
3 . The controller of claim 1 , wherein the controller is configured to supply the verification signal simultaneously with the address signal and the command signal.
4 . The controller of claim 1 , wherein the controller is further configured to:
receive an alert signal ALRT from the memory device wherein the alert signal is indicative that a verification error has occurred.
5 . The controller of claim 4 , wherein, responsive to receiving the alert signal ALRT, the controller is configured to read an error log from a mode register, the error log comprising an indication of an address signal ADD and a command signal CMD associated with the verification error.
6 . The controller of claim 5 , wherein the controller is configured to adjust a latency associated with reading the error log from the mode register.
7 . The controller of claim 1 , wherein the verification signal generation circuit is configured to:
set the verification signal PRTY to a low level if the number of high-level bits included in the plurality of bits constituting the address signal ADD and the command signal CMD is an even number; and
set the verification signal PRTY to a high level if the number of high-level bits included in the plurality of bits constituting the address signal ADD and the command signal CMD is an odd number.
8 . The controller of claim 1 , wherein the controller is further configured to:
supply a mode register setting command to the memory device, wherein the mode register setting command is indicative that the memory device should perform verification of the verification signal.
9 . A system comprising:
a controller; and
a memory device;
wherein the controller comprises:
a verification signal generation circuit configured to generate a verification signal PRTY based on an address signal ADD and a command signal CMD; and
an output circuit configured to supply a chip select signal CS, the address signal, the command signal and the verification signal to the memory device.
10 . The system of claim 9 , wherein the memory device comprises a verification circuit configured to:
determine whether a verification error has occurred; and
wherein responsive to determining that a verification error has occurred, the memory device is further configured to:
output an alert signal ALRT to the controller.
11 . The system of claim 10 , wherein the verification circuit is configured to:
determine whether a verification error has occurred based on the verification signal PRTY, the command signal CMD and the address signal ADD received from the controller.
12 . The system of claim 10 , wherein the controller is further configured to:
supply a mode register setting command to the memory device; and
wherein the memory device is further configured to determine whether a verification error has occurred in response to receiving the mode register setting command.
13 . The system of claim 10 , wherein outputting the alert signal ALRT to the controller comprises outputting an indication of an address signal ADD and a command signal CMD associated with the verification error.
14 . The system of claim 9 , wherein the verification signal is a parity signal, the parity signal being indicative of whether the address signal ADD and the command signal CMD comprise an even number of high level bits.
15 . The system of claim 9 , wherein the memory device is a DRAM.
16 . A method for controlling operation of a memory device, the method comprising:
a verification signal generation circuit of a memory controller generating a verification signal PRTY based on an address signal ADD and a command signal CMD; and
an output circuit of the memory controller supplying a chip select signal CS, the address signal ADD, the command signal CMD and the verification signal PRTY to the memory device.
17 . The method of claim 16 , wherein the output circuit of the controller supplies the verification signal PRTY simultaneously with the address signal ADD and the command signal CMD.
18 . The method of claim 16 , further comprising:
receiving an alert signal ALRT from the memory device wherein the alert signal is indicative that a verification error has occurred.
19 . The method of claim 18 , wherein, responsive to receiving the alert signal ALRT, the controller reads an error log from a mode register, the error log comprising an indication of an address signal ADD and a command signal CMD associated with the verification error.
20 . The method of claim 19 , wherein the controller adjusts a latency associated with reading the error log from the mode register.
21 . The method of claim 16 , wherein the verification signal generation circuit:
sets the verification signal PRTY to a low level if the number of high-level bits included in the plurality of bits constituting the address signal ADD and the command signal CMD is an even number; and
sets the verification signal PRTY to a high level if the number of high-level bits included in the plurality of bits constituting the address signal ADD and the command signal CMD is an odd number.
22 . The method of claim 16 , further comprising:
the controller supplying a mode register setting command to the memory device, wherein the mode register setting command is indicative that the memory device should perform verification of the verification signal.
23 . The method of claim 16 , further comprising a verification circuit of the memory device:
determining whether a verification error has occurred; and
responsive to determining that a verification error has occurred:
outputting an alert signal ALRT to the controller.
24 . The method of claim 23 , wherein the verification circuit:
determines whether a verification error has occurred based on the verification signal PRTY, the command signal CMD and the address signal ADD received from the controller.
25 . The method of claim 23 , further comprising:
the controller supplying a mode register setting command to the memory device; and
the memory device determining whether a verification error has occurred in response to receiving the mode register setting command.
26 . The method of claim 23 , wherein outputting the alert signal ALRT to the controller comprises outputting an indication of an address signal ADD and a command signal CMD associated with the verification error.
27 . The method of claim 16 , wherein the memory device is a DRAM.