Semiconductor device having PDA function
A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.
1. A method for operating a system comprising a controller and a plurality of memory devices, the method comprising:
providing at a first time a first mode register setting command, a first plurality of selection signals, and a first mode signal from the controller to the plurality of memory devices in common;
providing at a second time later than the first time a first enable signal having a first logic level from the controller to a first memory device of the plurality of memory devices and a second enable signal having a second logic level opposite the first logic level from the controller to a second memory device of the plurality of memory devices; and
storing the first mode signal in a first mode register selected by the first plurality of selection signals in the first memory device and not storing the first mode signal in a first mode register selected by the first plurality of selection signals in the second memory device.
2. The method as claimed in claim 1 , wherein the delay from the first time to the second time is a predetermined latency.
3. The method as claimed in claim 2 , wherein the predetermined latency is a write latency.
4. The method as claimed in claim 1 , wherein the first logic level is a low level and the second logic level is a high level.
5. The method as claimed in claim 1 , wherein the first and second enable signals are held at the second logic level between the first time and the second time.
6. The method as claimed in claim 1 , wherein the first plurality of selection signals are encoded selection signals.
7. The method as claimed in claim 1 , further comprising:
providing at a third time later than the first time a second mode register setting command, a second plurality of selection signals, and a second mode signal from the controller to the plurality of memory devices in common;
providing at a fourth time later than the third time a third enable signal having the second logic level from the controller to the first memory device and a fourth enable signal having the first logic level from the controller to the second memory device; and
storing the second mode signal in a second mode register selected by the second plurality of selection signals in the second memory device and not storing the second mode signal in a second mode register selected by the second plurality of selection signals in the second memory device.
8. The method as claimed in claim 7 , wherein the first enable signal changes from the first logic level to the second logic at a fifth time between the second time and the third time.
9. The method as claimed in claim 7 , wherein the second time is later than the third time.
10. The method as claimed in claim 7 , wherein the delay from the first time to the second time and the delay from the third time to the fourth time is a predetermined latency.
11. The method as claimed in claim 10 , wherein the predetermined latency is a write latency.
12. The method as claimed in claim 7 , wherein the first logic level is a low level and the second logic level is a high level.
13. The method as claimed in claim 1 , wherein the first and second enable signals are held at the second logic level between the first time and the second time and between the third time and the fourth time.
14. The method as claimed in claim 1 , wherein the first plurality of selection signals and the second plurality of selection signals are encoded selection signals.