IP Library Granted Patent US 10,673,320
Granted Patent B2
US 10,673,320 · App. 16/468,220 · Granted Jun 2, 2020

Snubber circuit and power conversion system including same

Inventors: Koji Higashiyama (Osaka, JP); Fumito Kusama (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H02M1/34H02M3/33584H02M7/5387H02M2001/342
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Quick Facts
Patent No.
US 10,673,320
App. No.
16/468,220
Granted
Jun 2, 2020
Kind
B2
Abstract

When a magnitude of a voltage between a pair of first voltage points in a main circuit exceeds a first clamp value, a first clamp circuit absorbs electrical energy of the main circuit from the pair of first voltage points to clamp the voltage to the first clamp value. When a magnitude of a voltage between a pair of second voltage points in the main circuit falls below a second clamp value, a second clamp circuit injects electrical energy to the main circuit from the pair of second voltage points to clamp the voltage to the second clamp value. A voltage conversion circuit performs voltage conversion between a first clamp voltage defining a first clamp value and a second clamp voltage defining a second clamp value.

Claims (39)

1. A snubber circuit comprising:

a first clamp circuit configured to, when a magnitude of a voltage between a pair of first voltage points in a main circuit exceeds a first clamp value, absorb electrical energy of the main circuit from the pair of first voltage points to clamp the voltage between the pair of the first voltage points to the first clamp value;

a second clamp circuit configured to, when a magnitude of a voltage between a pair of second voltage points in the main circuit falls below a second clamp value, inject electrical energy to the main circuit from the pair of second voltage points to clamp the voltage between the pair of the second voltage points to the second clamp value; and

a voltage conversion circuit electrically connected to the first clamp circuit and the second clamp circuit and configured to perform voltage conversion between a first clamp voltage and a second clamp voltage, the first clamp voltage defining the first clamp value, the second clamp voltage defining the second clamp value, wherein

one first voltage point of the pair of first voltage points is located on a high-potential side, one second voltage point of the pair of second voltage points is located on the high-potential side, and a potential at the one first voltage point is equal to a potential at the one second voltage point, and

the other first voltage point of the pair of first voltage points is located on a low-potential side, the other second voltage point of the pair of second voltage points is located on the low-potential side, and a potential at the other first voltage point is equal to a potential at the other second voltage point.

2. The snubber circuit of claim 1 , wherein

the voltage conversion circuit is a DC/DC converter including

a semiconductor switch,

an inductor, and

a capacitive element electrically connected in parallel to at least one of the semiconductor switch and the inductor.

3. The snubber circuit of claim 1 , wherein

the first clamp circuit includes a first diode and a first capacitive element which are electrically connected in series between the pair of first voltage points, the first clamp circuit is configured to, when the voltage between the pair of first voltage points exceeds the first clamp value, cause a current to flow from the main circuit through the first diode to the first capacitive element,

the second clamp circuit includes a second diode and a second capacitive element which are electrically connected in series between the pair of second voltage points, the second clamp circuit is configured to, when the voltage between the pair of second voltage points falls below the second clamp value, cause a current to flow from the second capacitive element through the second diode to the main circuit.

4. The snubber circuit of any claim 1 , wherein

the voltage conversion circuit is a DC/DC converter including

a semiconductor switch, and

an inductor, and

the voltage conversion circuit is configured to cause the semiconductor switch to perform switching operation such that an inductor current flowing through the inductor is in a discontinuous mode.

5. The snubber circuit of claim 1 , wherein

the voltage conversion circuit is a DC/DC converter including

a semiconductor switch,

an inductor, and

a control circuit configured to control the semiconductor switch,

the control circuit is configured to adjust a duty ratio of the semiconductor switch to adjust the first clamp value and the second clamp value.

6. A power conversion system, comprising:

the snubber circuit of claim 1 ; and

the main circuit,

the main circuit being a power conversion circuit configured to convert electric power.

7. The power conversion system of claim 6 , wherein

the main circuit includes

two or more primary-side terminals,

two or more secondary-side terminals, and

a high-frequency insulated transformer, and

the main circuit is configured to convert electric power between a set of the two or more primary-side terminals and a set of the two or more secondary-side terminals via the high-frequency insulated transformer.

8. The power conversion system of claim 7 , wherein the snubber circuit is electrically connected to the high-frequency insulated transformer.

9. The snubber circuit of claim 1 , wherein the first clamp voltage is higher than the second clamp voltage.

10. The snubber circuit of claim 9 , wherein

the voltage conversion circuit is configured to step down the first clamp voltage to generate the second clamp voltage.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2025
From: INFINEON TECHNOLOGIES AUSTRIA AG
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 072853/0508 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2024
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 069503/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2019
From: HIGASHIYAMA, KOJI; KUSAMA, FUMITO
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 051057/0409 →
Priority Claims (1)
JP 2016-240510 · Dec 12, 2016 · national
Continuity (1)
Related Publication 20190334430A1 · Oct 31, 2019
Cited By (1)
US 12,633,904