IP Library Granted Patent US 10,734,443
Granted Patent B2
US 10,734,443 · App. 16/507,538 · Granted Aug 4, 2020

Dual manetoresistance element with two directions of response to external magnetic fields

Inventors: Rémy Lassalle-Balier (Bures sur Yvette, FR); Paolo Campiglio (Arcueil, FR)
Assignee: Allegro MicroSystems, LLC
H01L27/22G01R33/09H01L43/02H01L43/08H01L43/10
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Quick Facts
Patent No.
US 10,734,443
App. No.
16/507,538
Granted
Aug 4, 2020
Kind
B2
Abstract

A material stack includes a first magnetoresistance element with a first direction of response to an external magnetic field and a second magnetoresistance element with second direction of response to the external magnetic field, opposite to the first direction of response. The first magnetoresistance element can be disposed under or over the second magnetoresistance element. An insulating layer separates the first and second magnetoresistance elements.

Claims (77)

1. An electronic circuit, comprising:

a first magnetoresistance element, comprising:

a first reference pinning layer having a first magnetic direction;

a first variable resistance layer; and

a first reference pinned layer disposed between the first reference pinning layer and the first variable resistance layer and proximate to the first variable-resistance layer, the first reference pinned layer having the first magnetic direction, the electronic circuit further comprising:

a second magnetoresistance element disposed under or over the first magnetoresistance element, comprising:

a second reference pinning layer having the first magnetic direction;

a second variable-resistance layer; and

a second reference pinned layer disposed between the second reference pinning layer and the second variable resistance layer and proximate to the second variable-resistance layer, the second reference pinned layer having a second magnetic direction opposite to the first magnetic direction, resulting in the first and second magnetoresistance elements having opposite responses to an external magnetic field.

2. The electronic circuit of claim 1 , further comprising:

a first insulator layer disposed between the first and second magnetoresistance elements.

3. The electronic circuit of claim 2 , wherein the first magnetoresistance element comprises:

a single synthetic antiferromagnetic (SAF) structure having the first reference pinned layer, wherein the second magnetoresistance element comprises:

a double synthetic antiferromagnetic (SAF) structure having the second reference pinned layer.

4. The electronic circuit of claim 3 , wherein the double synthetic antiferromagnetic (SAF) structure comprises:

first, second, and third ferromagnetic layers, the third ferromagnetic layer being the first reference pinned layer;

a first spacer layer disposed between the first and second ferromagnetic layers, the first spacer layer having a thickness and a material selected to result in antiferromagnetic coupling between the first and second ferromagnetic layers; and

a second spacer layer disposed between the second and third antiferromagnetic layers, the second spacer layer having a thickness and a material selected to result in antiferromagnetic coupling between the first and second ferromagnetic layers to result in the first and third ferromagnetic layers having the same internal magnetic direction.

5. The electronic circuit of claim 3 , wherein the single synthetic antiferromagnetic (SAF) structure comprises fourth and fifth ferromagnetic layers, the fifth ferromagnetic layer being the second pinned reference layer; and

a third spacer layer disposed between the fourth and fifth ferromagnetic layers, the third spacer layer having a thickness and a material selected to result in antiferromagnetic coupling between the fourth and fifth ferromagnetic layers.

6. The electronic circuit of claim 3 , further comprising:

a first free layer structure disposed proximate to the first reference pinned layer structure; and

a second free layer structure disposed proximate to the second reference pinned layer structure; wherein, in the absence of an external magnetic field, the first and second free layer structures have opposite directions of internal magnetic fields, resulting in the first and second magnetoresistance elements having opposite directions of response to the external magnetic field.

7. The electronic circuit of claim 3 , wherein the first and second magnetoresistance elements are coupled together in a half bridge arrangement.

8. The electronic circuit of claim 3 , wherein the first and second magnetoresistance elements are Giant Magnetoresistance (GMR) elements.

9. The electronic circuit of claim 3 , wherein the first and second magnetoresistance elements are Tunneling Magnetoresistance (TMR) elements.

10. The electronic circuit of claim 3 , wherein the first and second magnetoresistance elements are TMR elements that have maximum response axes perpendicular to a substrate on which the first and second magnetoresistance elements are formed.

11. The electronic circuit of claim 2 , wherein the first magnetoresistance element comprises:

a pinned layer structure having the first reference pinned layer, wherein the second magnetoresistance element comprises:

a single synthetic antiferromagnetic (SAF) structure having the second reference pinned layer.

12. The electronic circuit of claim 11 , wherein the pinned layer structure comprises:

the first reference pinned layer.

13. The electronic circuit of claim 11 , wherein the single synthetic antiferromagnetic (SAF) structure comprises first and second ferromagnetic layers, the first ferromagnetic layer being the second pinned reference layer; and

a spacer layer disposed between the first and second ferromagnetic layers, the spacer layer having a thickness and a material selected to result in antiferromagnetic coupling between the first and second ferromagnetic layers.

14. The electronic circuit of claim 11 , further comprising:

a first free layer structure disposed proximate to the first reference pinned layer structure; and

a second free layer structure disposed proximate to the second reference pinned layer structure; wherein, in the absence of an external magnetic field, the first and second free layer structures have opposite directions of internal magnetic fields, resulting in the first and second magnetoresistance elements having opposite directions of response to the external magnetic field.

15. The electronic circuit of claim 11 , wherein the first and second magnetoresistance elements are coupled together in a half bridge arrangement.

16. The electronic circuit of claim 11 , wherein the first and second magnetoresistance elements are GMR elements.

17. The electronic circuit of claim 11 , wherein the first and second magnetoresistance elements are TMR elements.

18. The electronic circuit of claim 11 , wherein the first and second magnetoresistance elements are TMR elements that have maximum response axes perpendicular to a substrate on which the first and second magnetoresistance elements are formed.

19. The electronic circuit of claim 11 , further comprising:

a third magnetoresistance element, comprising:

a third reference pinning layer having a third magnetic direction;

a third variable-resistance layer; and

a third reference pinned layer disposed between the third reference pinning layer and the third variable-resistance layer and proximate to the third variable-resistance layer, the third reference pinned layer having the third magnetic direction, the electronic circuit further comprising:

a fourth magnetoresistance element disposed under or over the third magnetoresistance element, comprising:

a fourth reference pinning layer having a fourth magnetic direction,

a fourth variable-resistance layer; and

a fourth reference pinned layer disposed between the fourth reference pinning layer and the fourth variable-resistance layer and proximate to the fourth variable-resistance layer, the fourth reference pinned layer having a fourth magnetic direction opposite to the third magnetic direction, resulting in the third and fourth magnetoresistance elements having opposite responses to an external magnetic field, the electronic circuit further comprising:

a second insulator layer disposed between the second and third magnetoresistance elements; and

a third insulator layer disposed between the third and fourth magnetoresistance elements.

20. The electronic circuit of claim 19 , wherein the first, second, third and fourth magnetoresistance elements are GMR elements.

21. The electronic circuit of claim 19 , wherein the first, second, third and fourth magnetoresistance elements are TMR elements.

22. The electronic circuit of claim 19 , wherein the first and second magnetoresistance elements are GMR elements and wherein the third and fourth magnetoresistance elements are TMR elements.

23. The electronic circuit of claim 19 , wherein the first and second magnetoresistance elements are GMR elements that have maximum response axes parallel to a substrate on which the first and second magnetoresistance elements are formed, and wherein the third and fourth magnetoresistance elements are TMR elements that have maximum response axes perpendicular to the substrate on which the third and fourth magnetoresistance elements are formed.

24. An electronic circuit, comprising:

a first magnetoresistance element, comprising:

a first single synthetic antiferromagnet (SAF) reference pinned layer structure having a first one and only one spacer layer having a material and a thickness to result in antiferromagnetic coupling across the first one and only one spacer layer;

a second magnetoresistance element disposed under or over the first magnetoresistance element, comprising:

a first double synthetic antiferromagnet (SAF) reference pinned layer structure having a first two and only two spacer layers, each having a respective material and a respective thickness to result in antiferromagnetic coupling across each one of the first two and only two spacer layers, the first signal synthetic antiferromagnet (SAF) resulting in the first magnetoresistance element having a first resistance change in a first direction and the first double synthetic antiferromagnet (SAF) resulting in the second magnetoresistance element having a second resistance change in a second direction opposite to the first direction in response to an external magnetic field, the electronic circuit further comprising:

a first insulator layer disposed between the first and second magnetoresistance elements.

25. The electronic circuit of claim 24 , wherein the first and second magnetoresistance elements are coupled together in a half bridge arrangement.

26. The electronic circuit of claim 24 , wherein the first and second magnetoresistance elements are Giant Magnetoresistance (GMR) elements.

27. The electronic circuit of claim 24 , wherein the first and second magnetoresistance elements are Tunneling Magnetoresistance (TMR) elements.

28. The electronic circuit of claim 24 , wherein the first and second magnetoresistance elements are TMR elements that have maximum response axes perpendicular to a substrate on which the first and second magnetoresistance elements are formed.

29. The electronic circuit of claim 24 , further comprising:

a third magnetoresistance element, comprising:

a second single synthetic antiferromagnet (SAF) reference pinned layer structure having a second one and only one spacer layer having a material and a thickness to result in antiferromagnetic coupling across the second one and only one spacer layer;

a fourth magnetoresistance element disposed under or over the third magnetoresistance element, comprising:

a second double synthetic antiferromagnet (SAF) reference pinned layer structure having a second two and only two spacer layers, each having a respective material and a respective thickness to result in antiferromagnetic coupling across each one of the second two and only two spacer layers, the second signal synthetic antiferromagnet (SAF) resulting in the third magnetoresistance element having a third resistance change in a third direction and the second double synthetic antiferromagnet (SAF) resulting in the fourth magnetoresistance element having a fourth resistance change in a fourth direction opposite to the third direction in response to an external magnetic field, the electronic circuit further comprising:

a second insulator layer disposed between the second and third magnetoresistance elements; and

a third insulator layer disposed between the third and fourth magnetoresistance elements.

30. The electronic circuit of claim 29 , wherein the first, second, third and fourth magnetoresistance elements are GMR elements.

31. The electronic circuit of claim 29 , wherein the first, second, third and fourth magnetoresistance elements are TMR elements.

32. The electronic circuit of claim 29 , wherein the first and second magnetoresistance elements are GMR elements and wherein the third and fourth magnetoresistance elements are TMR elements.

33. The electronic circuit of claim 29 , wherein the first and second magnetoresistance elements are GMR elements that have maximum response axes parallel to a substrate on which the first and second magnetoresistance elements are formed, and wherein the third and fourth magnetoresistance elements are TMR elements that have maximum response axes perpendicular to the substrate on which the third and fourth magnetoresistance elements are formed.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 053957/FRAME 0874 Recorded Nov 1, 2023
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 065420/0572 →
RELEASE OF SECURITY INTEREST IN PATENTS (R/F 053957/0620) Recorded Jun 22, 2023
From: MIZUHO BANK, LTD., AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 064068/0360 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2023
From: ALLEGRO MICROSYSTEMS, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 064068/0459 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: MIZUHO BANK LTD., AS COLLATERAL AGENT
Reel/Frame 053957/0620 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 053957/0874 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2019
From: LASSALLE-BALIER, RÉMY; CAMPIGLIO, PAOLO; ALLEGRO MICROSYSTEMS FRANCE SAS; ALLEGRO MICROSYSTEMS EUROPE LIMITED; CRIVASENSE TECHNOLOGIES SAS
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 049736/0118 →
Continuity (2)
Continuation In Part 16113321 · Aug 27, 2018
Related Publication 20200066790A1 · Feb 27, 2020
Cited By (6)
US 12,320,870 US 12,347,595 US 12,359,904 US 12,510,609 US 12,546,836 US 12,591,026