High-bandwidth STO bias architecture with integrated slider voltage potential control
Disclosed herein are circuits, architectures, and methods that provide for the control of a data storage device write head's trailing shield and main pole potential with respect to the disk using circuitry that is integrated with circuitry used to bias a spin torque oscillator (STO) apparatus. Various embodiments include slider connections with STO bias circuitry that resides in a read/write integrated circuit, which has a programmable circuit that generates a bias current with overshoot (bias kicks). Also disclosed are circuits that may be incorporated into a slider to mitigate radio-frequency interference.
1. A circuit for electrically biasing a spin-torque oscillator (STO), the circuit comprising:
a first operational transconductance amplifier (OTA);
a first low-pass filter coupled to an output of the first OTA and to a first input of the first OTA; and
a differential current source for providing a bias current to the STO, the differential current source having first and second outputs,
wherein:
a second input of the first OTA is coupled to a first node of a STO bias voltage source,
the output of the first OTA is coupled to a first node of the STO,
the first output of the differential current source is coupled to the first node of the STO, and
the second output of the differential current source is coupled to a second node of the STO.
2. The circuit recited in claim 1 , wherein the bias current comprises a low-frequency component and a kick current.
3. The circuit recited in claim 2 , wherein at least one characteristic of the low-frequency component or the kick current is programmable.
4. The circuit recited in claim 2 , wherein a voltage provided by the STO bias voltage source is based on a programmed value of the low-frequency component and a resistance of the STO.
5. The circuit recited in claim 1 , further comprising:
an interface voltage control source, wherein a first node of the interface voltage control source is coupled to ground and a second node of the interface voltage control source is coupled to the first node of the STO bias voltage source.
6. The circuit recited in claim 1 , further comprising:
a first capacitor and a first termination resistance connected in series and disposed between and coupled to the second input of the first OTA and the first node of the STO.
7. The circuit recited in claim 1 , further comprising:
a second capacitor and a second termination resistance connected in series and disposed between and coupled to a second node of the STO bias voltage source.
8. The circuit recited in claim 1 , further comprising:
a first analog circuit configured to determine a resistance of the STO based on the STO bias voltage and a measured STO bias current.
9. The circuit recited in claim 8 , further comprising:
a second analog circuit configured to determine an amplitude of the STO bias kick current based on a voltage provided by the STO bias voltage source, a STO voltage kick target value, the resistance of the STO, and a termination resistance.
10. The circuit recited in claim 8 , further comprising:
firmware configured to determine an amplitude of the STO bias kick current based on a voltage provided by the STO bias voltage source, a STO voltage kick target value, the resistance of the STO, and a termination resistance.
11. A read/write head comprising the circuit recited in claim 1 .
12. A data storage device comprising the circuit recited in claim 1 .
13. The circuit recited in claim 1 , further comprising:
a second OTA; and
a second low-pass filter coupled to an output of the second OTA and to a first input of the second OTA,
wherein:
a second input of the second OTA is coupled to the STO bias voltage source,
the output of the second OTA is coupled to the second node of the STO, and
the STO bias voltage source is programmable.
14. The circuit recited in claim 13 , further comprising:
a capacitor and a termination resistance connected in series and disposed between and coupled to the second input of the second OTA and the second node of the STO.
15. The circuit recited in claim 13 , further comprising:
a first analog circuit configured to determine a resistance of the STO based on the STO bias voltage source and a measured STO bias current.
16. The circuit recited in claim 15 , further comprising:
a second analog circuit configured to determine an amplitude of the STO bias kick current based on a voltage provided by the STO bias voltage source, a STO voltage kick value, the resistance of the STO, and a termination resistance.
17. The circuit recited in claim 15 , further comprising:
firmware configured to determine the STO bias kick current based on a voltage provided by the STO bias voltage source, a STO voltage kick value, a resistance of the STO, and a termination resistance.
18. A read/write head comprising the circuit recited in claim 13 .
19. A data storage device comprising the circuit recited in claim 13 .