IP Library Granted Patent US 10,643,564
Granted Patent B2
US 10,643,564 · App. 16/557,767 · Granted May 5, 2020

Liquid crystal display and method of driving liquid crystal display

Inventors: Shinji Kawabuchi (Tokyo, JP); Manabu Tanahara (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
G09G3/3677G02F1/1368G02F1/136286G09G3/3648G02F2001/136254G09G2300/043G09G2300/0408G09G2310/0245G09G2310/0264G09G2310/0278G09G2320/0257G09G2330/021G09G2330/027
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,643,564
App. No.
16/557,767
Granted
May 5, 2020
Kind
B2
Abstract

A liquid crystal display includes scanning lines and signal lines arranged in a matrix pattern on a TFT substrate, a pixel being formed at a crossing portion of each scanning line and each signal line, and including a TFT that is connected to each scanning line and each signal line, first nonlinear resistance elements formed respectively in the scanning lines, each of which being connected to one scanning line at one end thereof and to a short ring power-supply line for a scanning line at another end thereof, and second nonlinear resistance elements formed respectively in the signal lines, each of which being connected to one signal line at one end thereof and to a short ring power-supply line for a signal line at another end thereof. A voltage is applied to the first and second nonlinear resistance elements independently of each scanning line and each signal line.

Claims (27)

1. A liquid crystal display, comprising:

a plurality of scanning lines and a plurality of signal lines arranged in a matrix pattern on a substrate;

a pixel being formed at a crossing portion of each of the plurality of scanning lines and each of the plurality of signal lines, and comprising a thin film transistor that is connected to each of the plurality of scanning lines and each of the plurality of signal lines;

a short ring line connected to each of the plurality of scanning lines and each of the plurality of signal lines;

inspection thin film transistors on a scanning line side that are formed respectively in the plurality of scanning lines;

an inspection scanning line arranged so as to be connected to each of the plurality of scanning lines through intermediation of each of the inspection thin film transistors on a scanning line side;

inspection thin film transistors on a signal line side that are formed respectively in the plurality of signal lines;

an inspection signal line arranged so as to be connected to each of the plurality of signal lines through intermediation of each of the inspection thin film transistors on a signal line side;

an inspection thin film transistor switching line on a scanning line side arranged so as to be connected to the inspection thin film transistors on a scanning line side; and

an inspection thin film transistor switching line on a signal line side arranged so as to be connected to the inspection thin film transistors on a signal line side, wherein

the inspection thin film transistor switching line on a scanning line side is configured to receive a voltage to turn on the inspection thin film transistors on a scanning line side,

when the inspection thin film transistors on a scanning line side are in an on state, the inspection scanning line is configured to receive a voltage to turn on all of the scanning lines,

the inspection thin film transistor switching line on a signal line side is configured to receive a voltage to turn on the inspection thin film transistors on a signal line side, and

when the inspection thin film transistors on a signal line side are in an on state, the inspection signal line is configured to receive a ground voltage.

2. The liquid crystal display according to claim 1 , further comprising:

a plurality of first nonlinear resistance elements formed respectively in the plurality of scanning lines, each of the plurality of first nonlinear resistance elements being connected to one of the plurality of scanning lines at one end thereof and being connected to the short ring line at another end thereof; and

a plurality of second nonlinear resistance elements formed respectively in the plurality of signal lines, each of the plurality of second nonlinear resistance elements being connected to one of the plurality of signal lines at one end thereof and being connected to the short ring line at another end thereof.

3. The liquid crystal display according to claim 1 , further comprising a scanning-line driving circuit for applying a voltage to each of the plurality of scanning lines,

wherein the scanning-line driving circuit is provided separately from the substrate.

4. The liquid crystal display according to claim 1 , further comprising a scanning-line driving circuit for applying a voltage to each of the plurality of scanning lines,

wherein the scanning-line driving circuit is provided on the substrate.

5. The liquid crystal display according to claim 1 , further comprising a signal-line driving circuit for applying a voltage to each of the plurality of signal lines,

wherein the signal-line driving circuit is provided separately from the substrate.

6. The liquid crystal display according to claim 1 , further comprising a signal-line driving circuit for applying a voltage to each of the plurality of signal lines,

wherein the signal-line driving circuit is provided on the substrate.

7. The liquid crystal display according to claim 1 , wherein an active layer of the thin film transistor comprises silicon as a main component thereof.

8. The liquid crystal display according to claim 1 , wherein an active layer of the thin film transistor comprises an oxide semiconductor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2021
From: MITSUBISHI ELECTRIC CORPORATION
To: TRIVALE TECHNOLOGIES
Reel/Frame 057651/0234 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2019
From: KAWABUCHI, SHINJI; TANAHARA, MANABU
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 050226/0901 →
Priority Claims (1)
JP 2016-235582 · Dec 5, 2016 · national
Continuity (2)
Division 15829108 · Dec 1, 2017
Related Publication 20190385559A1 · Dec 19, 2019