Methods and apparatus for an interface
Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage, bi-directional channel redriver having a transmitter and a receiver that share input pads and output pads. The interface may provide for selective biasing of the transmitter and receiver using a switching circuit and a resistance circuit connected to the channel's input and output pads.
1. An interface circuit, comprising:
a receiver and a transmitter, wherein the transmitter and receiver share:
a first pair of I/O pads; and
a second pair of I/O pads; and
at least one switching circuit connected to at least one of the first pair and second pair of I/O pads and configured to selectively bias the at least one pair of I/O pads according to a plurality of voltages.
2. The interface circuit according to claim 1 , further comprising a first resistance circuit and a second resistance circuit, wherein each of the first and second resistance circuits comprises a plurality of resistors.
3. The interface circuit according to claim 2 , wherein:
the first resistance circuit is directly connected to:
a first I/O pad from the first pair of I/O pads; and
a second I/O pad from the first pair of I/O pads; and
the second resistance circuit is directly connected to:
a first I/O pad from the second pair of I/O pads; and
a second I/O pad from the second pair of I/O pads.
4. The interface circuit according to claim 2 , wherein:
the first resistance circuit comprises:
a first resistive element connected to a second I/O pad from the first pair of I/O pads and
a second resistive element connected to a first I/O pad from the first pair of I/O pads; and
the second resistance circuit comprises:
a third resistive element connected to a first I/O pad from the second pair of I/O pads; and
a fourth resistive element connected to a second I/O pad from the second pair of I/O pads.
5. The interface circuit according to claim 1 , wherein each voltage from the plurality of voltages is less than 3.0 volts.
6. The interface circuit according to claim 1 , wherein the switching circuit comprises a plurality of switching devices.
7. The interface circuit according to claim 1 , further comprising:
a first switching circuit configured to connect the first pair of I/O pads to a first voltage from the plurality of voltages; and
a second switching circuit configured to connect the second pair of I/O pads to a second voltage from the plurality of voltages.
8. The interface circuit according to claim 1 , wherein the interface circuit is configured to operate in a high-speed mode and a power-saving mode.
9. The interface circuit according to claim 1 , wherein:
an input terminal of the transmitter and an output terminal of the receiver share a first pad from the first pair of I/O pads; and
an output terminal of the transmitter and an input terminal of the receiver share a first pad from the second pair of I/O pads.
10. A method for operating an interface circuit having a receiver and a transmitter, comprising:
activating the transmitter, comprising:
operating in a first mode, comprising:
biasing a first pair of I/O pads; and
biasing a second pair of I/O pads differently from the first pair of I/O pads;
operating in a second mode, comprising:
equally biasing the first pair of I/O pads and second pair of I/O pads;
activating the receiver, comprising:
operating in the first mode, comprising:
biasing the first pair of I/O pads; and
biasing the second pair of I/O pads differently from the first pair of I/O pads;
operating in the second mode, comprising:
equally biasing the first pair of I/O pads and the second pair of I/O pads;
wherein the receiver and transmitter share the first pair of the I/O pads and the second pair of I/O pads.
11. The method according to claim 10 , wherein equally biasing the first pair of I/O pads and the second pair of I/O pads comprises selectively operating a first switching device to connect the first and second pairs of I/O pads to a same voltage.
12. The method according to claim 10 , wherein biasing the second pair of I/O pads differently from the first pair of I/O pads comprises:
selectively operating a first switching device to connect the first pair of I/O pads to first voltage; and
selectively operating a second switching device to connect the second pair of I/O pads to a second voltage.
13. The method according to claim 12 , wherein the first and second voltages are less than 3.0 volts.
14. The method according to claim 10 , wherein the first mode is a high-speed mode and the second mode is a power-saving mode.
15. A system, comprising:
a host device connected to a sink device via an interface circuit, wherein the interface circuit comprises:
a channel comprising:
a first pair of I/O pads arranged at a first end of the channel; and
a second pair of I/O pads arranged at a second end of the channel;
a first resistance circuit connected to the first pair of I/O pads;
a second resistance circuit connected to the second pair of I/O pads; and
a first switching circuit connected to the first pair of I/O pads via the first resistance circuit and configured to selectively bias the first pair of I/O pads according to a plurality of voltages.
16. The system according to claim 15 , wherein:
the first resistance circuit comprises:
a first resistive element connected to a second I/O pad from the first pair of I/O pads and
a second resistive element connected to a first I/O pad from the first pair of I/O pads; and
the second resistance circuit comprises:
a third resistive element connected to a first I/O pad from the second pair of I/O pads; and
a fourth resistive element connected to a second I/O pad from the second pair of I/O pads.
17. The system according to claim 15 , wherein the channel comprises a uni-directional redriver circuit.
18. The system according to claim 15 , wherein the channel comprises a bi-directional redriver circuit comprising a transmitter connected in parallel with a receiver, wherein the transmitter and receiver share the first and second pairs of I/O pads.
19. The system according to claim 15 , further comprising a second switching circuit connected to the second pair of I/O pads via the second resistance circuit and configured to selectively bias the second pair of I/O pads according to the plurality of voltages.
20. The system according to claim 15 , wherein each voltage from the plurality of voltages is less than 3.0 volts.