IP Library Granted Patent US 11,056,480
Granted Patent B2
US 11,056,480 · App. 16/704,365 · Granted Jul 6, 2021

Method of forming a TVS semiconductor device

Inventors: Yupeng Chen (San Jose, CA); Steven M. Etter (Phoenix, AZ); Umesh Sharma (San Jose, CA)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L27/0248H01L23/535H01L27/0255H01L27/0259H01L27/0664H01L29/0804H01L29/0821H01L29/66136H01L29/66234H01L29/7322H01L29/861H01L29/8611H01L29/0638H01L29/0649H01L29/0692H01L29/1004H01L29/732H01L29/8613
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,056,480
App. No.
16/704,365
Granted
Jul 6, 2021
Kind
B2
Abstract

In one embodiment, a TVS semiconductor device includes a P-N diode that is connected in parallel with a bipolar transistor wherein a breakdown voltage of the bipolar transistor is less than a breakdown voltage of the P-N diode.

Claims (21)

1. A method of forming a transient voltage suppressor (TVS) semiconductor device comprising:

forming a P-N diode connected in parallel between a collector and an emitter of a bipolar transistor wherein a base of the bipolar transistor is floating and not directly connected externally to the bipolar transistor; and

forming a thickness of a first current carrying electrode of the P-N diode to be greater than a total thickness of the base of the bipolar transistor wherein a reverse breakdown voltage of the P-N diode is to be greater than an open base collector-to-emitter breakdown voltage of the bipolar transistor (BVeco).

2. The method of claim 1 including forming an anode of the P-N diode commonly connected to one of the collector or the emitter of the bipolar transistor and to a first terminal of the TVS semiconductor device, and forming a cathode of the P-N diode commonly connected to a different one of the collector or the emitter of the bipolar transistor and to a second terminal of the TVS semiconductor device.

3. The method of claim 1 including forming an anode of the P-N diode commonly connected to the emitter of the bipolar transistor and to a first terminal of the TVS semiconductor device, and forming a cathode of the P-N diode commonly connected to the collector of the bipolar transistor and to a second terminal of the TVS semiconductor device.

4. The method of claim 1 including forming at least a portion of the P-N diode and at least a portion of the bipolar transistor in a semiconductor region having a first conductivity type that is overlying a substrate of a second conductivity type, wherein the portion of the P-N diode is a first portion of the semiconductor region and the portion of the bipolar transistor is a second portion of the semiconductor region that is isolated from the first portion of the semiconductor region.

5. The method of claim 1 further including forming a semiconductor region having a first conductivity type including forming the semiconductor region overlying a substrate of a second conductivity type;

forming the first current carrying electrode of the P-N diode as a first portion of the semiconductor region; and

forming the base of the bipolar transistor as a second portion of the semiconductor region.

6. The method of claim 5 further including forming an isolation region between the first portion of the semiconductor region and the second portion of the semiconductor region.

7. The method of claim 1 further including forming the base to be a first portion of a first doped region that has a first conductivity type and forming the first current carrying electrode to be a second portion of the first doped region.

8. A method of forming a transient voltage suppressor (TVS) semiconductor device comprising:

forming a P-N diode connected in parallel between a collector and an emitter of a bipolar transistor wherein a base of the bipolar transistor is floating and not directly connected externally to the bipolar transistor; and

forming a thickness of a first current carrying electrode of the P-N diode to be greater than a thickness of the base of the bipolar transistor including forming the base as a first doped region having a first doping concentration and forming the emitter as a second doped region having a second doping concentration that is less than the first doping concentration wherein the second doped region overlies the first doped region wherein a reverse breakdown voltage of the P-N diode is to be greater than an open base collector-to-emitter breakdown voltage of the bipolar transistor (BVeco).

9. A method of forming a transient voltage suppressor (TVS) semiconductor device comprising:

providing a substrate of a first conductivity type;

forming a doped region of a second conductivity type on the substrate;

forming at least a portion of a bipolar transistor in a first portion of the doped region wherein a base of the bipolar transistor is floating and not directly connected externally to the bipolar transistor, and wherein a collector-base junction of the bipolar transistor is formed at an interface between the substrate and the first portion of the doped region;

forming a least a portion of a diode in a second portion of the doped region wherein a total thickness of the second portion is substantially the same as a total thickness of the first portion, and wherein a P-N junction of the diode is formed at an interface between the substrate and the second portion of the doped region; and

forming the diode connected in parallel between a collector and an emitter of the bipolar transistor.

10. The method of claim 9 further including forming a first doping concentration of the first portion of the doped region to be substantially the same as a second doping concentration of the second portion of the doped region.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2019
From: CHEN, YUPENG; ETTER, STEVEN M.; SHARMA, UMESH
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 051190/0710 →
Continuity (2)
Continuation 15684556 · Aug 23, 2017
Related Publication 20200111777A1 · Apr 9, 2020