Semiconductor device
A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.
1. A semiconductor device, comprising:
a semiconductor substrate;
a first wiring pattern formed over the semiconductor substrate and extending in a first direction as viewed from a top view, the first wiring pattern having a first width in a second direction perpendicular to the first direction;
a first dummy pattern, a first space and a second dummy pattern arranged consecutively in a third direction and occupying a first area, wherein the third direction is different from the second direction, the first dummy pattern having a second maximum length in the first direction and a second maximum width in the second direction, the second dummy pattern having a third maximum length in the first direction and a third maximum width in the second direction, wherein no pattern is formed between the first dummy pattern and the second dummy pattern in the third direction; and
a third dummy pattern placed near the first wiring pattern and extending in a fourth direction, the third dummy pattern having a fourth length in the first direction and a fourth width in the second direction, at least a portion of the third dummy pattern is disposed in an area between the first dummy pattern and the first wiring pattern in the second direction, and at least another portion of the third dummy pattern is disposed in an area between the second dummy pattern and the wiring pattern in the second direction, wherein the fourth length is longer than the second maximum length and the third maximum length, and the fourth width is smaller than the second maximum width and the third maximum width;
wherein the first, second and third dummy patterns have a same level as that of the first wiring pattern, an interlayer insulating film formed between the first wiring pattern and the semiconductor substrate;
wherein each of the first and second dummy patterns is adjacent to the third dummy pattern without any pattern therebetween in the second direction; and
wherein no other pattern is formed between the first wiring pattern and the first area in the second direction.
2. The semiconductor device of claim 1 , wherein the first and the second dummy patterns have a same shape and size.
3. The semiconductor device of claim 2 , the first and second dummy patterns having a same orientation.
4. The semiconductor device of claim 3 , a fourth dummy patterns having a same shape, size and orientation as the first and second dummy patterns repeatedly arranged in the third direction.
5. The semiconductor device of claim 4 , further comprising a plurality of fifth dummy patterns having a same pattern and orientation as the first dummy pattern repeatedly arranged in a fourth direction orthogonal to the third direction.
6. The semiconductor device of claim 5 , wherein the plurality of the first, second, fourth and fifth dummy patterns are arranged in a matrix in the third and fourth directions.
7. The semiconductor device of claim 6 , wherein each dummy pattern in the matrix is separated from the adjacent dummy pattern in the third direction by a first minimum spacing in the first direction, each dummy pattern in the matrix is separated from the adjacent dummy pattern in the fourth direction by a second minimum spacing in the second direction, wherein the first minimum spacing is substantially identical to the second minimum spacing.
8. The semiconductor device of claim 7 , wherein the third dummy pattern having a pattern edge facing the first wiring pattern, wherein the pattern edge of the third dummy pattern extending along a virtual line in the first direction, wherein no portion of the matrix can extend into a second area between the virtual line and the first area in the second direction.
9. The semiconductor device of claim 1 , wherein the first direction is same as the third direction, the third dummy pattern is separated from the first dummy pattern by a first minimum spacing in the second direction, the third dummy pattern is separated from the wiring pattern by a second minimum spacing in the second direction, wherein the first and second minimum spacings are the same.
10. The semiconductor device of claim 1 , the third dummy pattern is separated from the first dummy pattern by a first minimum spacing in the second direction, the third dummy pattern is separated from the wiring pattern by a second minimum spacing in the second direction, wherein the first minimum spacing is smaller than the second minimum spacing.
11. The semiconductor device of claim 1 , wherein the third direction is different from the first direction.
12. The semiconductor device of claim 1 , wherein the third direction is same as the first direction.
13. The semiconductor device of claim 12 , wherein the third direction is different from the first direction.
14. The semiconductor device of claim 12 , wherein the third direction is same as the first direction.
15. The semiconductor device of claim 1 , wherein the first width is larger than the fourth width.
16. A semiconductor device, comprising:
a first wiring pattern formed over the semiconductor substrate and extending in a first direction as viewed from a top view, the first wiring pattern having a first width in a second direction perpendicular to the first direction;
a first dummy pattern, a first space and a second dummy pattern occupies a first area and arranged consecutively in this order in a third direction, wherein the third direction is different from the second direction, the first dummy pattern having a second maximum length in the first direction and a second maximum width in the second direction, the second dummy pattern having a third maximum length in the first direction and a third maximum width in the second direction, the first space having no pattern formed therein; and
a third dummy pattern placed near the first wiring pattern and extending in a first direction, the third dummy pattern having a fourth length in the first direction and a fourth width in the second direction, the third dummy pattern at least partially overlaps with both of the first and second dummy patterns in the second direction, wherein the fourth length is longer than the second maximum length and the third maximum length;
wherein the first, second and third dummy patterns have a same level as that of the first wiring pattern, an interlayer insulating film formed between the first wiring pattern and the semiconductor substrate;
wherein each of the first and second dummy patterns is adjacent to the third dummy pattern without any pattern therebetween in the second direction;
wherein no other dummy pattern is between the first wiring pattern and the first area in the second direction; and
wherein none of the first dummy pattern or second dummy pattern in their original orientation can fit into the third dummy pattern.